公开(公告)号：US20210335616A1

公开(公告)日：2021-10-28

申请号：US17370684

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Ying LIN ,  Cheng-Yi WU ,  Alan TU ,  Chung-Liang CHENG ,  Li-Hsuan CHU ,  Ethan HSIAO ,  Hui-Lin SUNG ,  Sz-Yuan HUNG ,  Sheng-Yung LO ,  C.W. CHIU ,  Chih-Wei HSIEH ,  Chin-Szu LEE

IPC: H01L21/285 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.

公开(公告)号：US20200006639A1

公开(公告)日：2020-01-02

申请号：US16210226

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang WU ,  Jui-Hung HO ,  Chin-Szu LEE ,  Meng-Yu WU ,  Szu-Hua WU

IPC: H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US20210288249A1

公开(公告)日：2021-09-16

申请号：US17334536

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang WU ,  Jui-Hung HO ,  Chin-Szu LEE ,  Meng-Yu WU ,  Szu-Hua WU

IPC: H01L45/00 ,  H01L43/02 ,  H01L21/768 ,  H01L43/12 ,  H01L23/532

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US20200043739A1

公开(公告)日：2020-02-06

申请号：US16596617

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Ying LIN ,  Cheng-Yi WU ,  Alan TU ,  Chung-Liang CHENG ,  Li-Hsuan CHU ,  Ethan HSIAO ,  Hui-Lin SUNG ,  Sz-Yuan HUNG ,  Sheng-Yung LO ,  C.W. CHIU ,  Chih-Wei Hsieh ,  Chin-Szu LEE

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/417 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.

公开(公告)号：US20230062902A1

公开(公告)日：2023-03-02

申请号：US17461147

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Chun HSIEH ,  Tsung-Yu TSAI ,  Hsing-Yuan HUANG ,  Chih-Chang WU ,  Szu-Hua WU ,  Chin-Szu LEE

IPC: C23C14/50 ,  H01L21/677 ,  C23C14/34 ,  H01L21/687

Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.

公开(公告)号：US20210336130A1

公开(公告)日：2021-10-28

申请号：US17168974

申请日：2021-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Jen CHIEN ,  Jung-Tang WU ,  Szu-Hua WU ,  Chin-Szu LEE ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20170358446A1

公开(公告)日：2017-12-14

申请号：US15180255

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi WU ,  Tzu-Shin Chen ,  Che-Kang Liu ,  Chi-Shun Wang ,  Chin-Szu LEE ,  Chia-Chun HUNG ,  Li-Hsuan CHU

IPC: H01L21/02 ,  G21K5/08

Abstract: A wafer processing apparatus includes at least one pedestal, at least one ultraviolet (UV) light source, and a window. The pedestal is configured to support a wafer. The UV light source is configured to generate UV radiation to the wafer. The window is present between the pedestal and the UV light source. The UV radiation is capable of passing through the window, and the window is a convex lens, a concave lens, or combinations thereof.

公开(公告)号：US20170084620A1

公开(公告)日：2017-03-23

申请号：US14857362

申请日：2015-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi WU ,  Jian-Shin TSAI ,  Kuo-Hsien CHENG ,  Min-Hui LIN ,  Wei-Li CHEN ,  Chao-Ching CHANG ,  Chung-Yu HSIEH ,  Chin-Szu LEE

IPC: H01L27/112 ,  H01L27/105

CPC classification number: H01L27/11206 ,  H01L23/5252

Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.