公开(公告)号：US20200006639A1

公开(公告)日：2020-01-02

申请号：US16210226

申请日：2018-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang WU ,  Jui-Hung HO ,  Chin-Szu LEE ,  Meng-Yu WU ,  Szu-Hua WU

IPC: H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US20230062902A1

公开(公告)日：2023-03-02

申请号：US17461147

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Chun HSIEH ,  Tsung-Yu TSAI ,  Hsing-Yuan HUANG ,  Chih-Chang WU ,  Szu-Hua WU ,  Chin-Szu LEE

IPC: C23C14/50 ,  H01L21/677 ,  C23C14/34 ,  H01L21/687

Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.

公开(公告)号：US20210336130A1

公开(公告)日：2021-10-28

申请号：US17168974

申请日：2021-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Jen CHIEN ,  Jung-Tang WU ,  Szu-Hua WU ,  Chin-Szu LEE ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20210119120A1

公开(公告)日：2021-04-22

申请号：US17112861

申请日：2020-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

公开(公告)号：US20200152864A1

公开(公告)日：2020-05-14

申请号：US16741557

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.

公开(公告)号：US20230073308A1

公开(公告)日：2023-03-09

申请号：US17984066

申请日：2022-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

公开(公告)号：US20210288249A1

公开(公告)日：2021-09-16

申请号：US17334536

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang WU ,  Jui-Hung HO ,  Chin-Szu LEE ,  Meng-Yu WU ,  Szu-Hua WU

IPC: H01L45/00 ,  H01L43/02 ,  H01L21/768 ,  H01L43/12 ,  H01L23/532

Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.

公开(公告)号：US20190164826A1

公开(公告)日：2019-05-30

申请号：US15964430

申请日：2018-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Pao-Sheng CHEN ,  Pei-Hsuan LEE ,  Szu-Hua WU ,  Chih-Chien CHI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.

公开(公告)号：US20190157548A1

公开(公告)日：2019-05-23

申请号：US16059777

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang WU ,  Szu-Ping TUNG ,  Szu-Hua WU ,  Shing-Chyang PAN ,  Meng-Yu WU

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.