公开(公告)号：US20240363752A1

公开(公告)日：2024-10-31

申请号：US18766402

申请日：2024-07-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Sin WANG ,  Shan-Yun CHENG ,  Ching-Hung KAO ,  Jing-Jyu CHOU ,  Yi-Ting CHEN

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/267 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/267 ,  H01L29/66545

摘要： A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

公开(公告)号：US20220285554A1

公开(公告)日：2022-09-08

申请号：US17751618

申请日：2022-05-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Sin WANG ,  Shan-Yun CHENG ,  Ching-Hung KAO ,  Jing-Jyu CHOU ,  Yi-Ting CHEN

IPC分类号： H01L29/78 ,  H01L29/267 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

摘要： A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

公开(公告)号：US20200328125A1

公开(公告)日：2020-10-15

申请号：US16914655

申请日：2020-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han TSAI ,  Po-Jen WANG ,  Chun-Li WU ,  Ching-Hung KAO

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/16 ,  H01L29/51

摘要： A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

公开(公告)号：US20220310528A1

公开(公告)日：2022-09-29

申请号：US17838375

申请日：2022-06-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Hung LEE ,  Chih-Fei LEE ,  Fu-Cheng CHANG ,  Ching-Hung KAO

IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

摘要： A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

公开(公告)号：US20210066498A1

公开(公告)日：2021-03-04

申请号：US16821690

申请日：2020-03-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Sin WANG ,  Shan-Yun CHENG ,  Ching-Hung KAO ,  Jing-Jyu CHOU ,  Yi-Ting CHEN

IPC分类号： H01L29/78 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092

摘要： A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

公开(公告)号：US20200083092A1

公开(公告)日：2020-03-12

申请号：US16686124

申请日：2019-11-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Hua YEN ,  Ching-Hung KAO ,  Po-Jen WANG ,  Tsung-Han TSAI

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/311 ,  H01L21/306 ,  H01L27/12 ,  H01L29/06

摘要： A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.

公开(公告)号：US20190067124A1

公开(公告)日：2019-02-28

申请号：US15692072

申请日：2017-08-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han TSAI ,  Po-Jen WANG ,  Chun-Li WU ,  Ching-Hung KAO

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/16 ,  H01L29/51

摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate. The substrate includes a first semiconductor layer, a second semiconductor layer, and an insulating layer between the first semiconductor layer and the second semiconductor layer. The semiconductor device structure also includes a gate stack over the substrate. The semiconductor device structure further includes source and drain structures in the second semiconductor layer of the substrate. The source and drain structures are on opposite sides of the gate stack. In addition, the semiconductor device structure includes a first isolation feature in the substrate. The first isolation feature includes an insulation material and surrounds the source and drain structures. The semiconductor device structure also includes a second isolation feature in the first isolation feature. The second isolation feature includes a metal material and surrounds the source and drain structures.

公开(公告)号：US20170179037A1

公开(公告)日：2017-06-22

申请号：US15158402

申请日：2016-05-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kuo-Hung LEE ,  Chih-Fei LEE ,  Fu-Cheng CHANG ,  Ching-Hung KAO

IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/544 ,  H01L21/78 ,  H01L23/5223 ,  H01L23/528 ,  H01L28/40 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446

摘要： A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

公开(公告)号：US20210159066A1

公开(公告)日：2021-05-27

申请号：US17169499

申请日：2021-02-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yao-Wen HSU ,  Ching-Hung KAO ,  Po-Jen WANG ,  Tsung-Han TSAI

IPC分类号： H01L21/02 ,  H01L21/683 ,  H01L21/687 ,  H01L21/67 ,  H01L21/22

摘要： A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

公开(公告)号：US20210028120A1

公开(公告)日：2021-01-28

申请号：US17068033

申请日：2020-10-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

发明人： Kuo-Hung LEE ,  Chih-Fei LEE ,  Fu-Cheng CHANG ,  Ching-Hung KAO

IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02

摘要： A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.