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公开(公告)号:US11450757B2
公开(公告)日:2022-09-20
申请号:US17013615
申请日:2020-09-06
发明人: Yu-Chang Lin , Chun-Feng Nieh , Huicheng Chang , Wei-Ting Chien , Chih-Pin Tsao , Hou-Ju Li , Tien-Shun Chang
IPC分类号: H01L29/66 , H01L21/8238 , H01L29/78 , H01L27/092 , H01L21/225 , H01L21/324 , H01L29/08
摘要: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
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公开(公告)号:US11264380B2
公开(公告)日:2022-03-01
申请号:US16112943
申请日:2018-08-27
发明人: Hou-Ju Li , Chur-Shyang Fu , Chun-Sheng Liang , Jeng-Ya David Yeh
IPC分类号: H01L27/088 , H01L29/08 , H01L21/762 , H01L21/8234 , H01L21/3105 , H01L21/3213
摘要: A semiconductor device includes a substrate, a first active fin, a second active fin, a dummy fin and a first gate structure. The first and the second active fin are on the substrate and extend along a first direction. The dummy fin is disposed between the first active fin and the second active fin, and extends in the first direction. The dummy fin includes a plurality of layers, and each of the layers includes a material different from another layer. The first gate structure crosses over the dummy fin, the first and the second active fins.
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公开(公告)号:US11776911B2
公开(公告)日:2023-10-03
申请号:US17330834
申请日:2021-05-26
发明人: Hung-Ming Chen , Yu-Chang Lin , Chung-Ting Li , Jen-Hsiang Lu , Hou-Ju Li , Chih-Pin Tsao
IPC分类号: H01L29/66 , H01L29/78 , H01L23/535 , H01L21/768 , H01L29/417
CPC分类号: H01L23/535 , H01L21/76841 , H01L21/76897 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7848
摘要: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.
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公开(公告)号:US11024582B2
公开(公告)日:2021-06-01
申请号:US15489905
申请日:2017-04-18
发明人: Hung-Ming Chen , Yu-Chang Lin , Chung-Ting Li , Jen-Hsiang Lu , Hou-Ju Li , Chih-Pin Tsao
IPC分类号: H01L29/76 , H01L23/535 , H01L29/66 , H01L29/78 , H01L21/768 , H01L29/417
摘要: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.
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公开(公告)号:US20180301417A1
公开(公告)日:2018-10-18
申请号:US15489905
申请日:2017-04-18
发明人: Hung-Ming Chen , Yu-Chang Lin , Chung-Ting Li , Jen-Hsiang Lu , Hou-Ju Li , Chih-Pin Tsao
IPC分类号: H01L23/535 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/768
摘要: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.
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