公开(公告)号：US20210200930A1

公开(公告)日：2021-07-01

申请号：US17204275

申请日：2021-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen LIN ,  Ming-Hsien LIN ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: G06F30/398 ,  G06F30/394

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

公开(公告)号：US20190108306A1

公开(公告)日：2019-04-11

申请号：US16214243

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen LIN ,  Ming-Hsien LIN ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: G06F17/50

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

公开(公告)号：US20220336272A1

公开(公告)日：2022-10-20

申请号：US17232083

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Lung HOU ,  Ming-Hsien LIN ,  Che-I KUO ,  Yung Hsin LU

IPC: H01L21/768 ,  C25D3/38 ,  C25D5/02

Abstract: An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

公开(公告)号：US20210241999A1

公开(公告)日：2021-08-05

申请号：US17141751

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Cheng WU ,  Sheng-Ying WU ,  Ming-Hsien LIN ,  Chun Fu CHEN

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/3213 ,  H01L21/3205

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

公开(公告)号：US20210238741A1

公开(公告)日：2021-08-05

申请号：US17119436

申请日：2020-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Cheng WU ,  Sheng-Ying WU ,  Ming-Hsien LIN

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/458

Abstract: An assembly includes a cover ring having a first surface and a second surface opposite the first surface, the first surface of the cover ring having a first roughness, and a deposition ring having a first surface facing the cover ring and a second surface opposite the first surface, the first surface of the deposition ring having a second roughness. The first roughness is different from the second roughness.

公开(公告)号：US20190120700A1

公开(公告)日：2019-04-25

申请号：US16142934

申请日：2018-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Ming-Hsien LIN ,  Anthony OATES

IPC: G01K7/01 ,  G01K3/00 ,  H01L27/02 ,  G11C7/04

Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

公开(公告)号：US20180144087A1

公开(公告)日：2018-05-24

申请号：US15355410

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen LIN ,  Ming-Hsien LIN ,  Kuo-Nan YANG ,  Chung-Hsing WANG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F17/5077

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

公开(公告)号：US20220336211A1

公开(公告)日：2022-10-20

申请号：US17232937

申请日：2021-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Lung HOU ,  Ming-Hsien LIN

IPC: H01L21/02 ,  C25D21/12 ,  C25D7/12 ,  C25D5/54 ,  H01L21/67 ,  H01L21/288 ,  H01L21/66 ,  B08B3/08 ,  B08B3/02 ,  B08B13/00

Abstract: An electrochemical plating apparatus for performing an edge bevel removal process on a wafer includes a cell chamber. The cell chamber includes two or more nozzles located adjacent to the edge of the wafer. A flow regulator is arranged with each of the two or more nozzles, which is configured to regulate an tap width of a deposited film flowing out through the each of the two or more nozzles. The electrochemical plating apparatus further includes a controller to control the flow regulator such that tap width of the deposited film includes a pre-determined surface profile. The two or more nozzles are located in radially or angularly different dispensing positions above the wafer.

公开(公告)号：US20220310362A1

公开(公告)日：2022-09-29

申请号：US17214656

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Cheng WU ,  Sheng-Ying WU ,  Ming-Hsien LIN

IPC: H01J37/32 ,  H01J37/34 ,  C23C14/35

Abstract: A processing chamber includes a ground shield and a cover ring. The ground shield includes an annular body, and at least one guide pin extending from the annular body. The cover ring is positioned on the ground shield, and includes an annular body including at least one recess. At least a part of the at least one guide pin is receivable in the at least one recess, an inner cylindrical ring extends from the annular body, and an outer cylindrical ring extends from the annular body and is radially separated from the inner cylindrical ring by a horizontally extending portion of the annular body.

公开(公告)号：US20210134616A1

公开(公告)日：2021-05-06

申请号：US16749286

申请日：2020-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Che CHEN ,  Wen-Tane LIAO ,  Ming-Hsien LIN ,  Wei-Chen LIAO ,  Hai-Lin LEE ,  Chun-Yu CHEN

IPC: H01L21/67

Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.