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    OPTIMIZED ELECTROMIGRATION ANALYSIS
    2.
    发明申请
    OPTIMIZED ELECTROMIGRATION ANALYSIS 审中-公开

    公开(公告)号：US20200050735A1

    公开(公告)日：2020-02-13

    申请号：US16659134

    申请日：2019-10-21

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chin-Shen LIN ,  Ching-Shun Yang ,  Hsien Yu-Tseng

    IPC分类号： G06F17/50

    摘要： A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

    POWER RAIL FOR PREVENTING DC ELECTROMIGRATION
    5.
    发明申请
    POWER RAIL FOR PREVENTING DC ELECTROMIGRATION 有权
    用于防止直流电机的电源

    公开(公告)号：US20150095864A1

    公开(公告)日：2015-04-02

    申请号：US14098435

    申请日：2013-12-05

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chin-Shen LIN ,  Jerry Chang-Jui KAO ,  Nitesh KATTA ,  Chou-Kun LIN ,  Yi-Chuin TSAI ,  Chi-Yeh YU ,  Kuo-Nan YANG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/82 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

    摘要翻译： 公开了一种包括以下概述的操作的方法。 当金属片段的第一端和第二端周围的第一电流和第二电流的方向分别相反时，第一标准被确定为满足，其中金属片段是至少一个中的电源轨的一部分 半导体器件的设计文件，仅由两个端子通孔阵列封装。 当金属段的长度不大于电迁移临界长度时，确定满足第二标准。 当符合第一和第二标准时，金属段被包括在半导体器件中，具有取决于金属段的长度的第一电流密度极限。

    EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD
    6.
    发明申请
    EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD 审中-公开
    EDA工具和方法，以及通过该方法形成的集成电路

    公开(公告)号：US20140229902A1

    公开(公告)日：2014-08-14

    申请号：US14258299

    申请日：2014-04-22

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Hsien YU-TSENG ,  Shih-Kai LIN ,  Chin-Shen LIN ,  Yu-Sian JIANG ,  Heng-Kai LIU ,  Mu-Jen HUANG ,  Chien-Wen CHEN

    IPC分类号： G06F17/50

    CPC分类号： H01L23/528 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/76816 ,  H01L23/53228 ,  H01L27/0207

    摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

    摘要翻译： 一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。 对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，至少N-1个针脚被插入到该组内的每个多边形中以将每个多边形分成至少N个部分，例如 不同多边形的相邻部分被分配给彼此不同的光掩模。 表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。

    METHOD FOR EVALUATING FAILURE-IN-TIME
    7.
    发明申请
    METHOD FOR EVALUATING FAILURE-IN-TIME 有权

    公开(公告)号：US20210200930A1

    公开(公告)日：2021-07-01

    申请号：US17204275

    申请日：2021-03-17

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chin-Shen LIN ,  Ming-Hsien LIN ,  Kuo-Nan YANG ,  Chung-Hsing WANG

    IPC分类号： G06F30/398 ,  G06F30/394

    摘要： A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

    METHOD, SYSTEM AND COMPUTER READABLE MEDIUM USING STITCHING FOR MASK ASSIGNMENT OF PATTERNS
    9.
    发明申请
    METHOD, SYSTEM AND COMPUTER READABLE MEDIUM USING STITCHING FOR MASK ASSIGNMENT OF PATTERNS 审中-公开
    方法，系统和计算机可读介质使用纹理分配掩模

    公开(公告)号：US20160240474A1

    公开(公告)日：2016-08-18

    申请号：US15139615

    申请日：2016-04-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Hsien YU-TSENG ,  Shih-Kai LIN ,  Chin-Shen LIN ,  Yu-Sian JIANG ,  Heng-Kai LIU ,  Mu-Jen HUANG ,  Chien-Wen CHEN

    IPC分类号： H01L23/528 ,  G06F17/50 ,  H01L21/768 ,  H01L27/02 ,  H01L23/532

    CPC分类号： H01L23/528 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/76816 ,  H01L23/53228 ,  H01L27/0207

    摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

    摘要翻译： 一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。 对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，至少N-1个针脚被插入到该组内的每个多边形中以将每个多边形分成至少N个部分，例如 不同多边形的相邻部分被分配给彼此不同的光掩模。 表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。