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    PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY
    1.
    发明申请
    PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY 有权
    性能敏感阵列的性能驱动和梯级密码插入

    公开(公告)号：US20140189625A1

    公开(公告)日：2014-07-03

    申请号：US13727691

    申请日：2012-12-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Mu-Jen Huang ,  Hsiao-Hui Chen ,  Cheok-Kei Lei ,  Po-Tsun Chen ,  Yu-Sian Jiang

    IPC: G06F17/50 ,  H01L27/02

    CPC classification number: H01L27/0207 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/11803 ,  Y02P90/265

    Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

    Abstract translation: 本公开涉及用于高密度阵列单元的性能感知缓冲区放置的布置和方法。 测量阵列的第一特征密度，并确定单位单元内的参数的最大变化。 参考硅数据查找表来预测缓冲区宽度和梯度值，其实现小于单元的最大变化的变化。 查找表包含一组各种阵列和缓冲区几何的硅测试案例，其中测量各个测试结构内的参数的变化并针对各种缓冲区几何进行编目，并且还从硅套件外推 测试用例。 缓冲区被放置在阵列的边界，其宽度小于或等于缓冲区宽度。

    Performance-driven and gradient-aware dummy insertion for gradient-sensitive array
    4.
    发明授权
    Performance-driven and gradient-aware dummy insertion for gradient-sensitive array 有权
    用于梯度敏感数组的性能驱动和渐变感知虚拟插入

    公开(公告)号：US08978000B2

    公开(公告)日：2015-03-10

    申请号：US13727691

    申请日：2012-12-27

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Mu-Jen Huang ,  Hsiao-Hui Chen ,  Cheok-Kei Lei ,  Po-Tsun Chen ,  Yu-Sian Jiang

    IPC: G06F9/455 ,  G06F17/50 ,  H01L27/02 ,  G03F1/00

    CPC classification number: H01L27/0207 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/11803 ,  Y02P90/265

    Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

    Abstract translation: 本公开涉及用于高密度阵列单元的性能感知缓冲区放置的布置和方法。 测量阵列的第一特征密度，并确定单位单元内的参数的最大变化。 参考硅数据查找表来预测缓冲区宽度和梯度值，其实现小于单元的最大变化的变化。 查找表包含一组各种阵列和缓冲区几何的硅测试案例，其中测量各个测试结构内的参数的变化并针对各种缓冲区几何进行编目，并且还从硅套件外推 测试用例。 缓冲区被放置在阵列的边界，其宽度小于或等于缓冲区宽度。

    Method, system and computer readable medium using stitching for mask assignment of patterns
    6.
    发明授权
    Method, system and computer readable medium using stitching for mask assignment of patterns 有权
    方法，系统和计算机可读介质，使用拼接进行图案的掩模分配

    公开(公告)号：US09342646B2

    公开(公告)日：2016-05-17

    申请号：US14258299

    申请日：2014-04-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien Yu-Tseng ,  Shih-Kai Lin ,  Chin-Shen Lin ,  Yu-Sian Jiang ,  Heng-Kai Liu ,  Mu-Jen Huang ,  Chien-Wen Chen

    IPC: G06F17/50

    CPC classification number: H01L23/528 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/76816 ,  H01L23/53228 ,  H01L27/0207

    Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

    Abstract translation: 一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。 对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，至少N-1个针脚被插入到该组内的每个多边形中以将每个多边形分成至少N个部分，例如 不同多边形的相邻部分被分配给彼此不同的光掩模。 表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。

    PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY
    7.
    发明申请
    PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY 有权
    性能敏感阵列的性能驱动和梯级密码插入

    公开(公告)号：US20150179627A1

    公开(公告)日：2015-06-25

    申请号：US14638065

    申请日：2015-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Mu-Jen Huang ,  Hsiao-Hui Chen ,  Cheok-Kei Lei ,  Po-Tsun Chen ,  Yu-Sian Jiang

    IPC: H01L27/02 ,  H01L27/118

    CPC classification number: H01L27/0207 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/11803 ,  Y02P90/265

    Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

    Abstract translation: 本公开涉及用于高密度阵列单元的性能感知缓冲区放置的布置和方法。 测量阵列的第一特征密度，并确定单位单元内的参数的最大变化。 参考硅数据查找表来预测缓冲区宽度和梯度值，其实现小于单元的最大变化的变化。 查找表包含一组各种阵列和缓冲区几何的硅测试案例，其中测量各个测试结构内的参数的变化并针对各种缓冲区几何进行编目，并且还从硅套件外推 测试用例。 缓冲区被放置在阵列的边界，其宽度小于或等于缓冲区宽度。

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