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    Power rail for preventing DC electromigration
    2.
    发明授权
    Power rail for preventing DC electromigration 有权
    用于防止直流电迁移的电源轨

    公开(公告)号：US09165882B2

    公开(公告)日：2015-10-20

    申请号：US14098435

    申请日：2013-12-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chi-Yeh Yu ,  Kuo-Nan Yang

    IPC: G06F9/455 ,  G06F17/50 ,  H01L23/522

    CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/82 ,  H01L23/5226 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

    Abstract translation: 公开了一种包括以下概述的操作的方法。 当金属片段的第一端和第二端周围的第一电流和第二电流的方向分别相反时，第一标准被确定为满足，其中金属片段是至少一个中的电源轨的一部分 半导体器件的设计文件，仅由两个端子通孔阵列封装。 当金属段的长度不大于电迁移临界长度时，确定满足第二标准。 当符合第一和第二标准时，金属段被包括在半导体器件中，具有取决于金属段的长度的第一电流密度极限。

    Electromigration sign-off tool
    3.
    发明授权
    Electromigration sign-off tool 有权

    公开(公告)号：US10719652B2

    公开(公告)日：2020-07-21

    申请号：US16460063

    申请日：2019-07-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F30/392 ,  H01L21/768 ,  G06F30/367 ,  G06F30/398 ,  G01R31/28

    Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

    Power grid of integrated circuit
    5.
    发明授权
    Power grid of integrated circuit 有权

    公开(公告)号：US09852989B1

    公开(公告)日：2017-12-26

    申请号：US15397036

    申请日：2017-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Shen Lin ,  Min-Yuan Tsai ,  Kuo-Nan Yang ,  Chung-Hsing Wang

    IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L23/5286 ,  H01L23/5226

    Abstract: Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power traces disposed in a second metal layer and parallel to a second direction that is perpendicular to the first direction, and third power traces disposed in the first metal layer parallel to the first direction. The first power traces arranged in the same straight line are separated from each other by a plurality of first gaps. The third power traces arranged in the same straight line are separated from each other by a plurality of second gaps. Each first gap is surrounded by the two adjacent third power traces. Each second gap is surrounded by the two adjacent first power traces. The first power traces are coupled to the third power traces via the second power traces.

    Metal lines for preventing AC electromigration
    6.
    发明授权
    Metal lines for preventing AC electromigration 有权
    用于防止交流电迁移的金属线

    公开(公告)号：US09152751B2

    公开(公告)日：2015-10-06

    申请号：US14267537

    申请日：2014-05-01

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chin-Shen Lin ,  Jerry Chang-Jui Kao ,  Nitesh Katta ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Kuo-Nan Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/76 ,  G06F2217/78 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

    Abstract translation: 公开了一种包括以下概述的操作的方法。 基于在半导体器件的至少一个设计文件中的金属线的金属部分的波形周期内具有多个峰值的电流的波形函数来确定最大峰值的有效电流脉冲宽度，以计算半导体器件的至少一个设计文件中的占空比 有效电流脉冲宽度和波形周期。 根据金属段的物理特性确定金属段的最大直流极限。 根据最大直流限制和占空比函数之间的比例来确定交流电流（AC EM）电流限制。 当电流的最大峰值不超过AC EM电流限制时，金属部分包括在至少一个设计文件中的物理特性。

    Electromigration sign-off tool
    8.
    发明授权
    Electromigration sign-off tool 有权

    公开(公告)号：US11182528B2

    公开(公告)日：2021-11-23

    申请号：US16929503

    申请日：2020-07-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F30/392 ,  H01L21/768 ,  G06F30/367 ,  G06F30/398 ,  G01R31/28

    Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

    ELECTROMIGRATION SIGN-OFF TOOL
    9.
    发明申请
    ELECTROMIGRATION SIGN-OFF TOOL 审中-公开

    公开(公告)号：US20200342156A1

    公开(公告)日：2020-10-29

    申请号：US16929503

    申请日：2020-07-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F30/392 ,  H01L21/768 ,  G06F30/367 ,  G06F30/398

    Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

    ELECTROMIGRATION SIGN-OFF TOOL
    10.
    发明申请
    ELECTROMIGRATION SIGN-OFF TOOL 审中-公开

    公开(公告)号：US20190325105A1

    公开(公告)日：2019-10-24

    申请号：US16460063

    申请日：2019-07-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Tseng Hsien ,  Chin-Shen Lin ,  Ching-Shun Yang ,  Jui-Feng Kuan

    IPC: G06F17/50 ,  H01L21/768

    Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

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