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公开(公告)号：US20230394219A1
公开(公告)日：2023-12-07
申请号：US18448149
申请日：2023-08-10
发明人： Fong-Yuan CHANG , Chin-Chou LIU , Hui-Zhong ZHUANG , Meng-Kai HSU , Pin-Dai SUE , Po-Hsiang HUANG , Yi-Kan CHENG , Chi-Yu LU , Jung-Chou TSAI
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F2119/18
摘要： A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US20150052492A1
公开(公告)日：2015-02-19
申请号：US13967913
申请日：2013-08-15
发明人： Yuan-Te HOU , Wen-Hao CHEN , Chin-Hsiung HSU , Meng-Kai HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F1/36 , G03F1/70 , G03F7/70283 , G03F7/70466
摘要： A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.
摘要翻译： 一种方法包括生成可用于实现集成电路的导电路径的一个或多个路由。 根据第一成本函数计算一个或多个路线的对应成本函数值，包括基于通过第一图案化处理至少部分地分配要在导电层中形成的相应路线来调整相应的成本函数值 或第二图案化工艺。 集成电路具有电气装置和导电层，并且导电层具有由第一构图工艺形成的第一组导电线和由第二构图工艺形成的第二组导电线。 第一组导线的单位电阻小于第二组导线的单位电阻。 导电路径电连接集成电路的两个电气装置。
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公开(公告)号：US20220216270A1
公开(公告)日：2022-07-07
申请号：US17140441
申请日：2021-01-04
发明人： Meng-Kai HSU , Jerry Chang Jui KAO , Chin-Shen LIN , Ming-Tao YU , Tzu-Ying LIN , Chung-Hsing WANG
摘要： An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
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公开(公告)号：US20220198121A1
公开(公告)日：2022-06-23
申请号：US17690990
申请日：2022-03-09
发明人： Anurag VERMA , Meng-Kai HSU , Chih-Wei CHANG
IPC分类号： G06F30/398
摘要： A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.
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公开(公告)号：US20200004912A1
公开(公告)日：2020-01-02
申请号：US16441802
申请日：2019-06-14
发明人： Meng-Kai HSU , Sheng-Hsiung CHEN , Wai-Kei MAK , Ting-Chi WANG , Yu-Hsiang CHENG , Ding-Wei HUANG
摘要： A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.
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6.发明申请公开(公告)号：US20180004886A1
公开(公告)日：2018-01-04
申请号：US15471146
申请日：2017-03-28
发明人： Prasenjit RAY , Lee-Chung LU , Meng-Kai HSU , Wen-Hao CHEN , Yuan-Te HOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5081 , H01L23/52 , H01L27/027
摘要： A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array. Each standard second array includes a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The method further includes: adding, to the M(N+Q) layer, second segments which connect corresponding first segments of the M(N+Q) metallization layer in the corresponding second standard arrays.
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公开(公告)号：US20200380194A1
公开(公告)日：2020-12-03
申请号：US16997703
申请日：2020-08-19
发明人： Meng-Kai HSU , Sheng-Hsiung CHEN , Wai-Kei MAK , Ting-Chi WANG , Yu-Hsiang CHENG , Ding-Wei HUANG
IPC分类号： G06F30/392 , G03F1/70 , G06F30/398
摘要： A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.
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公开(公告)号：US20190286784A1
公开(公告)日：2019-09-19
申请号：US16299973
申请日：2019-03-12
发明人： Fong-Yuan CHANG , Chin-Chou LIU , Hui-Zhong ZHUANG , Meng-Kai HSU , Pin-Dai SUE , Po-Hsiang HUANG , Yi-Kan CHENG , Chi-Yu LU , Jung-Chou TSAI
IPC分类号： G06F17/50
摘要： A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US20220382957A1
公开(公告)日：2022-12-01
申请号：US17885106
申请日：2022-08-10
发明人： Fong-Yuan CHANG , Chin-Chou LIU , Hui-Zhong ZHUANG , Meng-Kai HSU , Pin-Dai SUE , Po-Hsiang HUANG , Yi-Kan CHENG , Chi-Yu LU , Jung-Chou TSAI
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394
摘要： A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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10.发明申请公开(公告)号：US20190108305A1
公开(公告)日：2019-04-11
申请号：US16206751
申请日：2018-11-30
发明人： Prasenjit RAY , Lee-Chung LU , Meng-Kai HSU , Wen-Hao CHEN , Yuan-Te HOU
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5081 , H01L23/52 , H01L23/5226 , H01L27/027
摘要： A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.
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