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    Photonic device and method of making same
    2.
    发明授权
    Photonic device and method of making same 有权

    公开(公告)号：US11892678B2

    公开(公告)日：2024-02-06

    申请号：US17412930

    申请日：2021-08-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Ying Wu ,  Yuehying Lee ,  Sui-Ying Hsu ,  Chen-Hao Huang ,  Chien-Chang Lee ,  Chia-Ping Lai

    IPC分类号： G02B6/12 ,  G02B6/30 ,  G02B6/34

    CPC分类号： G02B6/12 ,  G02B6/30 ,  G02B6/34

    摘要： A photonic device includes a silicon layer, wherein the silicon layer extends from a waveguide region of the photonic device to a device region of the photonic device, and the silicon layer includes a waveguide portion in the waveguide region. The photonic device further includes a cladding layer over the waveguide portion, wherein the device region is free of the cladding layer. The photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. The photonic device further includes an interconnect structure over the low refractive index layer.

    Capacitor device and manufacturing method thereof
    4.
    发明授权
    Capacitor device and manufacturing method thereof 有权

    公开(公告)号：US11776896B2

    公开(公告)日：2023-10-03

    申请号：US17219282

    申请日：2021-03-31

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jen-Yuan Chang ,  Chia-Ping Lai ,  Chien-Chang Lee

    IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L23/532

    CPC分类号： H01L23/5223 ,  H01L23/53266 ,  H01L28/91

    摘要： Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.

    Fiber to chip coupler and method of making the same
    5.
    发明授权
    Fiber to chip coupler and method of making the same 有权

    公开(公告)号：US12050348B2

    公开(公告)日：2024-07-30

    申请号：US18448032

    申请日：2023-08-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chen-Hao Huang ,  Hau-Yan Lu ,  Sui-Ying Hsu ,  Yuehying Lee ,  Chien-Ying Wu ,  Chien-Chang Lee ,  Chia-Ping Lai

    IPC分类号： G02B6/34 ,  G02B6/30 ,  G02B6/42

    CPC分类号： G02B6/34 ,  G02B6/30 ,  G02B6/4204

    摘要： A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.

    INTERPOSER WITH WARPAGE-RELIEF TRENCHES
    10.
    发明申请
    INTERPOSER WITH WARPAGE-RELIEF TRENCHES 有权

    公开(公告)号：US20220344280A1

    公开(公告)日：2022-10-27

    申请号：US17547218

    申请日：2021-12-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tsung-Yang Hsieh ,  Chien-Chang Lee ,  Chia-Ping Lai ,  Wen-Chung Lu ,  Cheng-Kang Huang ,  Mei-Shih Kuo ,  Alice Huang

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

    摘要： A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.