公开(公告)号：US20230352594A1

公开(公告)日：2023-11-02

申请号：US17732552

申请日：2022-04-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yen-Sheng LU ,  Chung-Chi WEN ,  Yen-Ting CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Chih-Chiang CHANG ,  Chien-I KUO ,  Yuan-Ching PENG ,  Chih-Ching WANG ,  Wen-Hsing Hsieh ,  Chii-Horng LI ,  Yee-Chia YEO

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

摘要： Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.

公开(公告)号：US20220271171A1

公开(公告)日：2022-08-25

申请号：US17184245

申请日：2021-02-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Chang SU ,  Yan-Ting LIN ,  Chien-Wei LEE ,  Bang-Ting YAN ,  Chih Teng HSU ,  Chih-Chiang CHANG ,  Chien-I KUO ,  Chii-Horng LI ,  Yee-Chia YEO

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

摘要： A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

公开(公告)号：US20240194788A1

公开(公告)日：2024-06-13

申请号：US18585422

申请日：2024-02-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Chang SU ,  Yan-Ting LIN ,  Chien-Wei LEE ,  Bang-Ting YAN ,  Chih Teng HSU ,  Chih-Chiang CHANG ,  Chien-I KUO ,  Chii-Horng LI ,  Yee-Chia YEO

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78696

摘要： A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

公开(公告)号：US20230343855A1

公开(公告)日：2023-10-26

申请号：US18340454

申请日：2023-06-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Hao LU ,  Chien-I KUO ,  Li-Li SU ,  Wei-Yang LEE ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/40

CPC分类号： H01L29/66636 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/823475 ,  H01L29/41733 ,  H01L29/401 ,  H01L21/823418 ,  H01L29/66545

摘要： A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

公开(公告)号：US20230317791A1

公开(公告)日：2023-10-05

申请号：US17711707

申请日：2022-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yan-Ting LIN ,  Chien-I KUO ,  Chii-Horng LI ,  Yee-Chia YEO

IPC分类号： H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/42392 ,  H01L29/41 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78696

摘要： A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a direction normal to a top surface the (110)-orientated substrate and extending in a direction perpendicular to the direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

公开(公告)号：US20220328657A1

公开(公告)日：2022-10-13

申请号：US17225786

申请日：2021-04-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Hao LU ,  Chien-I KUO ,  LI-Li SU ,  Wei-Yang LEE ,  Yee-Chia YEO

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L29/40 ,  H01L21/8234

摘要： A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.