公开(公告)号：US09995998B2

公开(公告)日：2018-06-12

申请号：US15188753

申请日：2016-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Fan Chen ,  Tung-Heng Hsieh ,  Chin-Shan Hou ,  Yu-Bey Wu

IPC分类号： G03F1/36 ,  G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5068 ,  G06F17/5081

摘要： A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.

公开(公告)号：US09377680B2

公开(公告)日：2016-06-28

申请号：US14081615

申请日：2013-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Fan Chen ,  Tung-Heng Hsieh ,  Chin-Shan Hou ,  Yu-Bey Wu

IPC分类号： G03F1/36 ,  G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5068 ,  G06F17/5081

摘要： Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.

摘要翻译： 提供集成电路（IC）测试线布局。 布局在设备边界内部具有设备边界和主图案边界。 布局包括主图案边界内的至少一个主图案。 该布局还包括在主图案边界和装置边界之间的区域中的多个虚拟图案。 多个虚拟图案可以在光刻工艺中打印，并且以两个相邻的虚设图案之间的均匀间隔布置在环中。

公开(公告)号：US09111768B2

公开(公告)日：2015-08-18

申请号：US14486923

申请日：2014-09-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Yu Lu ,  Shyue-Shyh Lin ,  Chin-Shan Hou ,  Kuo-Feng Yu ,  Tung-Heng Hsieh ,  Chih-Hung Wang ,  Jian-Hao Chen

IPC分类号： H01L27/088 ,  H01L27/13 ,  H01L27/06 ,  H01L49/02 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L27/0629 ,  H01L21/76811 ,  H01L23/485 ,  H01L23/5228 ,  H01L27/0688 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.

摘要翻译： 公开了半导体器件，其制造方法和形成电阻器的方法。 在一个实施例中，制造半导体器件的方法包括在工件上形成第一绝缘材料，并在第一绝缘材料上形成导电化合物材料。 将导电化合物材料图案化以形成电阻器。 第二绝缘材料形成在电阻器上，第二绝缘材料被图案化。 图案化的第二绝缘材料填充有导电材料以形成耦合到电阻器的第一端的第一触点，并形成耦合到电阻器的第二端的第二触点。

公开(公告)号：US20160370698A1

公开(公告)日：2016-12-22

申请号：US15188753

申请日：2016-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Fan Chen ,  Tung-Heng Hsieh ,  Chin-Shan Hou ,  Yu-Bey Wu

IPC分类号： G03F1/36 ,  G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5068 ,  G06F17/5081

摘要： A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.

摘要翻译： 一种方法包括接收集成电路（IC）装置的布局，所述布局具有外边界和内边界，从而限定外边界和内边界之间的第一区域，并且在第一区域中放置第一多个虚拟图案 ，其中所述第一多个虚拟图案是可光学印刷的。 该方法还包括执行光学近程校正（OPC）过程，第一多个虚拟图案位于第一区域内，以防止通过OPC处理将子分辨率辅助特征插入第一区域。

公开(公告)号：US20150001678A1

公开(公告)日：2015-01-01

申请号：US14486923

申请日：2014-09-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Yu Lu ,  Shyue-Shyh Lin ,  Chin-Shan Hou ,  Kuo-Feng Yu ,  Tung-Heng Hsieh ,  Chih-Hung Wang ,  Jian-Hao Chen

IPC分类号： H01L27/06 ,  H01L49/02

CPC分类号： H01L27/0629 ,  H01L21/76811 ,  H01L23/485 ,  H01L23/5228 ,  H01L27/0688 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices, methods of manufacture thereof, and methods of forming resistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first insulating material over a workpiece, and forming a conductive chemical compound material over the first insulating material. The conductive chemical compound material is patterned to form a resistor. A second insulating material is formed over the resistor, and the second insulating material is patterned. The patterned second insulating material is filled with a conductive material to form a first contact coupled to a first end of the resistor and to form a second contact coupled to a second end of the resistor.

摘要翻译： 公开了半导体器件，其制造方法和形成电阻器的方法。 在一个实施例中，制造半导体器件的方法包括在工件上形成第一绝缘材料，并在第一绝缘材料上形成导电化合物材料。 将导电化合物材料图案化以形成电阻器。 第二绝缘材料形成在电阻器上，第二绝缘材料被图案化。 图案化的第二绝缘材料填充有导电材料以形成耦合到电阻器的第一端的第一触点，并形成耦合到电阻器的第二端的第二触点。