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    MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS
    1.
    发明申请
    MULTI-PORT SRAM CELL WITH DUAL SIDE POWER RAILS 有权

    公开(公告)号：US20240414907A1

    公开(公告)日：2024-12-12

    申请号：US18489365

    申请日：2023-10-18

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ping-Wei Wang ,  Jui-Lin Chen ,  Yu-Bey Wu

    IPC: H10B10/00

    Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively, and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. A first frontside source/drain contact is disposed above and electrically couples to a first common source/drain region of the first and second pull-down transistors. A first backside via is disposed under and electrically couples to the first common source/drain region. A first backside metal line is disposed under and electrically couples to the first backside via.

    Interconnect Structure for Front-to-Front Stacked Chips
    4.
    发明申请
    Interconnect Structure for Front-to-Front Stacked Chips 有权

    公开(公告)号：US20250046756A1

    公开(公告)日：2025-02-06

    申请号：US18404376

    申请日：2024-01-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Tsung-Chieh Hsiao ,  Yi Ling Liu ,  Ke-Gang Wen ,  Yu-Bey Wu ,  Liang-Wei Wang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58

    Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.

    METHOD AND APPARATUS FOR INTEGRATED CIRCUIT LAYOUT
    9.
    发明申请
    METHOD AND APPARATUS FOR INTEGRATED CIRCUIT LAYOUT 有权
    集成电路布局的方法和装置

    公开(公告)号：US20160370698A1

    公开(公告)日：2016-12-22

    申请号：US15188753

    申请日：2016-06-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yi-Fan Chen ,  Tung-Heng Hsieh ,  Chin-Shan Hou ,  Yu-Bey Wu

    IPC: G03F1/36 ,  G06F17/50

    CPC classification number: G03F1/36 ,  G06F17/5068 ,  G06F17/5081

    Abstract: A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.

    Abstract translation: 一种方法包括接收集成电路（IC）装置的布局，所述布局具有外边界和内边界，从而限定外边界和内边界之间的第一区域，并且在第一区域中放置第一多个虚拟图案 ，其中所述第一多个虚拟图案是可光学印刷的。 该方法还包括执行光学近程校正（OPC）过程，第一多个虚拟图案位于第一区域内，以防止通过OPC处理将子分辨率辅助特征插入第一区域。

    Static Random-Access Memory Device with Enhanced Isolation Structure and Increased Packing Density
    10.
    发明申请
    Static Random-Access Memory Device with Enhanced Isolation Structure and Increased Packing Density 有权

    公开(公告)号：US20250048613A1

    公开(公告)日：2025-02-06

    申请号：US18411620

    申请日：2024-01-12

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Lin Chen ,  Feng-Ming Chang ,  Ping-Wei Wang ,  Yu-Bey Wu

    IPC: H10B10/00

    Abstract: The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De/Ds equals to 2 or is less than 2.

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