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公开(公告)号：US10354952B2
公开(公告)日：2019-07-16
申请号：US14528337
申请日：2014-10-30
发明人： Hidehiro Fujiwara , Li-Wen Wang , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L27/11 , H01L23/528 , H01L23/522 , G06F17/50 , H01L27/02
摘要： A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line.
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公开(公告)号：US11783890B2
公开(公告)日：2023-10-10
申请号：US17816048
申请日：2022-07-29
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096 , G11C5/06 , G11C11/419 , H01L21/48 , H10B10/00
CPC分类号： G11C11/4094 , G11C5/063 , G11C7/12 , G11C11/4096 , G11C11/419 , H01L21/4889 , H10B10/18
摘要： A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).
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公开(公告)号：US10431295B2
公开(公告)日：2019-10-01
申请号：US14291443
申请日：2014-05-30
发明人： Li-Wen Wang , Chih-Yu Lin , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C7/00 , G11C11/417 , G11C11/419
摘要： A static random access memory (SRAM) that includes a memory cell comprising at least two p-type pass gates. The SRAM also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell.
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公开(公告)号：US09105326B2
公开(公告)日：2015-08-11
申请号：US14291162
申请日：2014-05-30
发明人： Yen-Huei Chen , Li-Wen Wang , Chih-Yu Lin
IPC分类号： G11C11/40 , G11C7/22 , G11C7/12 , G11C11/419
CPC分类号： G11C7/22 , G11C7/12 , G11C11/419
摘要： A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level.
摘要翻译： 写入存储单元的方法包括在写入周期期间使得存储单元的电源端子处的电压电平从电源电压电平变为第一电压电平。 存储单元的电源端子处的电压电平在第一预定持续时间内保持在第一电压电平。 存储单元的电源端子处的电压电平在第二预定持续时间内保持在第二电压电平，其中第二电压电平处于第一电压电平和电源电压电平之间。 在写周期期间，使存储单元的电源端子处的电压电平从第一电压电平变为电源电压电平。
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公开(公告)号：US10163491B2
公开(公告)日：2018-12-25
申请号：US15251260
申请日：2016-08-30
发明人： Hidehiro Fujiwara , Li-Wen Wang , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C8/14 , G11C11/419 , G11C11/418 , H01L27/02 , H01L27/11
摘要： A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.
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6.发明授权公开(公告)号：US10991420B2
公开(公告)日：2021-04-27
申请号：US16991449
申请日：2020-08-12
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096
摘要： A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
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公开(公告)号：US10783955B2
公开(公告)日：2020-09-22
申请号：US16207030
申请日：2018-11-30
发明人： Hidehiro Fujiwara , Li-Wen Wang , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L27/11 , G11C11/419 , G11C11/418 , H01L27/02 , G11C8/14
摘要： A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
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公开(公告)号：US09449661B2
公开(公告)日：2016-09-20
申请号：US14799780
申请日：2015-07-15
发明人： Yen-Huei Chen , Li-Wen Wang , Chih-Yu Lin
IPC分类号： G11C7/22 , G11C7/12 , G11C11/419
CPC分类号： G11C7/22 , G11C7/12 , G11C11/419
摘要： A memory device includes a memory cell electrically connected to a power line and a power supply unit configured to control a voltage level on the power line. The power supply unit receives a control signal corresponding to a write cycle of the memory cell and, responsive to a first state of the control signal, outputs a first voltage level on the power line. Responsive to a second state of the control signal, the power supply unit outputs a second voltage level on the power line, the second voltage level having a magnitude less than a magnitude of the first voltage level.
摘要翻译： 存储装置包括电连接到电力线的存储单元和被配置为控制电力线上的电压电平的电源单元。 电源单元接收对应于存储单元的写入周期的控制信号，并且响应于控制信号的第一状态在电力线上输出第一电压电平。 响应于控制信号的第二状态，电源单元在电力线上输出第二电压电平，第二电压电平具有小于第一电压电平的幅度的幅度。
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公开(公告)号：US11423974B2
公开(公告)日：2022-08-23
申请号：US17241687
申请日：2021-04-27
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096 , G11C5/06 , G11C11/419 , H01L21/48 , H01L27/11
摘要： A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.
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公开(公告)号：US11152301B2
公开(公告)日：2021-10-19
申请号：US16511997
申请日：2019-07-15
发明人： Hidehiro Fujiwara , Li-Wen Wang , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： H01L27/11 , H01L23/528 , H01L23/522 , H01L27/02 , G06F30/394
摘要： A method of designing a memory circuit is provided that includes generating a layout of a first memory cell using an integrated circuit design system. The layout of the first memory cell is generated by routing a first word line in a first layer on a first level, and routing a second word line in the first layer. Also, the method includes generating a layout of a second memory cell using the integrated circuit design system. The layout of the second memory cell is generated by routing a third word line in the first layer, the second word line being between the first word line and the third word line, and routing a fourth word line in the first layer, the third word line being between the second word line and the fourth word line. Moreover, the method includes assigning a first color scheme to the first word line and to the third word line, and assigning a second color scheme to the second word line and to the fourth word line. The first color scheme is associated with a first manufacturing process using a first mask and the second color scheme is associated with a second manufacturing process using a second mask.
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