公开(公告)号：US20210209284A1

公开(公告)日：2021-07-08

申请号：US17209918

申请日：2021-03-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jian-Sing LI ,  Hui-Zhong ZHUANG ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Ting-Wei CHIANG ,  Tzu-Ying LIN ,  Li-Chun TIEN

IPC分类号： G06F30/392 ,  H01L27/02

摘要： A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The first active region forms, together with the initial cell, a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. The positioning the first active region is executed by a processor.

公开(公告)号：US20230253961A1

公开(公告)日：2023-08-10

申请号：US18302178

申请日：2023-04-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Chen CHIEN ,  Xiangdong CHEN ,  Hui-Zhong ZHUANG ,  Tzu-Ying LIN ,  Jerry Chang Jui KAO ,  Lee-Chung LU

IPC分类号： H03K3/3562 ,  H03K3/037 ,  H03K3/012

CPC分类号： H03K3/35625 ,  H03K3/0372 ,  H03K3/012 ,  H03K3/0375

摘要： A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

公开(公告)号：US20210226615A1

公开(公告)日：2021-07-22

申请号：US17095191

申请日：2020-11-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hadi RASOULI ,  Jerry Chang Jui KAO ,  Xiangdong CHEN ,  Tzu-Ying LIN ,  Yung-Chen CHEN ,  Hui-Zhong ZHUANG ,  Chi-Lin LIU

IPC分类号： H03K3/037 ,  H03K19/20 ,  G06F1/12

摘要： A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

公开(公告)号：US20240097661A1

公开(公告)日：2024-03-21

申请号：US18152017

申请日：2023-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Huaixin XIAN ,  Tzu-Ying LIN ,  Liu HAN ,  Jerry Chang Jui KAO ,  Qingchao MENG ,  Xiangdong CHEN

IPC分类号： H03K3/037 ,  G01R31/3177 ,  G01R31/3185 ,  H03K19/00 ,  H03K19/0948

CPC分类号： H03K3/037 ,  G01R31/3177 ,  G01R31/318525 ,  G01R31/31855 ,  H03K19/0002 ,  H03K19/0948

摘要： A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.

公开(公告)号：US20240038762A1

公开(公告)日：2024-02-01

申请号：US18314536

申请日：2023-05-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hui-Zhong ZHUANG ,  Johnny Chiahoa LI ,  Tzu-Ying LIN ,  Jia-Hong GAO ,  Jung-Chan YANG ,  Jerry Chang Jui KAO

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L21/8238 ,  H03K3/037

CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L21/82385 ,  H01L21/823871 ,  H03K3/037 ,  H01L2027/11837 ,  H01L2027/11866

摘要： A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

公开(公告)号：US20230403868A1

公开(公告)日：2023-12-14

申请号：US18447614

申请日：2023-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jerry Chang Jui KAO ,  Meng-Kai HSU ,  Chin-Shen LIN ,  Ming-Tao YU ,  Tzu-Ying LIN ,  Chung-Hsing WANG

IPC分类号： H10K19/10 ,  H10K19/00

CPC分类号： H10K19/10 ,  H01L28/10 ,  H01L28/40 ,  H10K19/201

摘要： A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.

公开(公告)号：US20230387893A1

公开(公告)日：2023-11-30

申请号：US18362916

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Seid Hadi RASOULI ,  Jerry Chang Jui KAO ,  Xiangdong CHEN ,  Tzu-Ying LIN ,  Yung-Chen CHEN ,  Hui-Zhong ZHUANG ,  Chi-Lin LIU

IPC分类号： H03K3/037 ,  G06F1/12 ,  H03K19/20

CPC分类号： H03K3/037 ,  G06F1/12 ,  H03K19/20

摘要： A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

公开(公告)号：US20240364317A1

公开(公告)日：2024-10-31

申请号：US18768843

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Chen CHIEN ,  Xiangdong CHEN ,  Hui-Zhong ZHUANG ,  Tzu-Ying LIN ,  Jerry Chang Jui KAO ,  Lee-Chung LU

IPC分类号： H03K3/3562 ,  H03K3/012 ,  H03K3/037

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/0375

摘要： A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

公开(公告)号：US20230110352A1

公开(公告)日：2023-04-13

申请号：US18065327

申请日：2022-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Seid Hadi RASOULI ,  Jerry Chang Jui KAO ,  Xiangdong CHEN ,  Tzu-Ying LIN ,  Yung-Chen CHEN ,  Hui-Zhong ZHUANG ,  Chi-Lin LIU

IPC分类号： H03K3/037 ,  H03K19/20 ,  G06F1/12

摘要： A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

公开(公告)号：US20220239286A1

公开(公告)日：2022-07-28

申请号：US17338199

申请日：2021-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Chen CHIEN ,  Xiangdong CHEN ,  Hui-Zhong ZHUANG ,  Tzu-Ying LIN ,  Jerry Chang Jui KAO ,  Lee-Chung LU

IPC分类号： H03K3/037

摘要： A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.