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    METHODS OF MANUFACTURING FUSIBLE STRUCTURES
    2.
    发明申请
    METHODS OF MANUFACTURING FUSIBLE STRUCTURES 有权

    公开(公告)号：US20220384339A1

    公开(公告)日：2022-12-01

    申请号：US17885321

    申请日：2022-08-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shao-Ting WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Chung-I HUANG

    IPC分类号： H01L23/525 ,  H01L27/112

    摘要： A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

    SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20210082812A1

    公开(公告)日：2021-03-18

    申请号：US16573761

    申请日：2019-09-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Po-Hsiang HUANG ,  An-Jiao FU ,  Chih-Hao CHEN

    IPC分类号： H01L23/525 ,  H01L21/768 ,  H01L23/00

    摘要： A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

    MEMORY WITH SYMMETRIC READ CURRENT PROFILE
    6.
    发明申请
    MEMORY WITH SYMMETRIC READ CURRENT PROFILE 有权

    公开(公告)号：US20210343333A1

    公开(公告)日：2021-11-04

    申请号：US17375608

    申请日：2021-07-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yuhsiang CHEN ,  Shao-Yu CHOU ,  Chun-Hao CHANG ,  Min-Shin WU ,  Yu-Der CHIH

    IPC分类号： G11C11/419 ,  G11C11/418

    摘要： Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.

    READING MEMORY DATA
    7.
    发明申请
    READING MEMORY DATA 审中-公开
    读取存储器数据

    公开(公告)号：US20140247672A1

    公开(公告)日：2014-09-04

    申请号：US14276648

    申请日：2014-05-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jui-Jen WU ,  Shao-Yu CHOU

    IPC分类号： G11C7/12

    CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/14 ,  G11C11/08 ,  G11C11/412 ,  G11C11/419 ,  G11C19/06

    摘要： A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

    摘要翻译： 电路包括一个或多个存储器单元，与一个或多个存储器单元相关联的数据线，一个或多个参考单元，与一个或多个参考单元相关联的参考数据线，耦合到参考数据线的第一电路和 数据线和第二电路。 第一电路被配置为当基准数据线的电压电平达到跳变点时，基于数据线的电压电平输出第一逻辑值。 第二电路被配置为基于在到达跳变点的参考数据线的电压电平发生之前的数据线上的电压电平输出第二逻辑值，并且在发生之后输出第一逻辑值 参考数据线的电压电平达到跳变点。

    MEMORY CIRCUIT AND METHOD OF OPERATING SAME
    8.
    发明公开
    MEMORY CIRCUIT AND METHOD OF OPERATING SAME 审中-公开

    公开(公告)号：US20240096431A1

    公开(公告)日：2024-03-21

    申请号：US18522564

    申请日：2023-11-29

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chun-Hao CHANG ,  Gu-Huan LI ,  Shao-Yu CHOU

    IPC分类号： G11C17/18 ,  G11C17/16

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.

    ANTI-FUSE DEVICE AND METHOD
    9.
    发明公开
    ANTI-FUSE DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230157009A1

    公开(公告)日：2023-05-18

    申请号：US18156625

    申请日：2023-01-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Min-Shin WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Yao-Jen YANG

    IPC分类号： H10B20/20 ,  G11C17/18 ,  G11C17/16

    CPC分类号： H10B20/20 ,  G11C17/18 ,  G11C17/16

    摘要： An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.