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    METHODS OF MANUFACTURING FUSIBLE STRUCTURES
    1.
    发明申请
    METHODS OF MANUFACTURING FUSIBLE STRUCTURES 有权

    公开(公告)号：US20220384339A1

    公开(公告)日：2022-12-01

    申请号：US17885321

    申请日：2022-08-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shao-Ting WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Chung-I HUANG

    IPC分类号： H01L23/525 ,  H01L27/112

    摘要： A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

    SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20210082812A1

    公开(公告)日：2021-03-18

    申请号：US16573761

    申请日：2019-09-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Po-Hsiang HUANG ,  An-Jiao FU ,  Chih-Hao CHEN

    IPC分类号： H01L23/525 ,  H01L21/768 ,  H01L23/00

    摘要： A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE 审中-公开

    公开(公告)号：US20200058660A1

    公开(公告)日：2020-02-20

    申请号：US16533359

    申请日：2019-08-06

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG

    IPC分类号： H01L27/112 ,  H01L23/528 ,  H01L23/525 ,  G11C17/18 ,  G06F17/50 ,  G11C17/16

    摘要： A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING ANTI-FUSE CELL STRUCTURE 有权

    公开(公告)号：US20220328505A1

    公开(公告)日：2022-10-13

    申请号：US17851569

    申请日：2022-06-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Yao-Jen YANG

    IPC分类号： H01L27/112 ,  H01L23/528 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  G06F30/392

    摘要： A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

    CAPACITOR AND METHOD FOR FORMING THE SAME
    5.
    发明申请
    CAPACITOR AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220328470A1

    公开(公告)日：2022-10-13

    申请号：US17225722

    申请日：2021-04-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Han LIN ,  Meng-Sheng CHANG

    IPC分类号： H01L27/02 ,  H01L21/82

    摘要： An integrated circuit (IC) structure includes a semiconductor substrate, a shallow trench isolation (STI) region, and a capacitor. The STI region is embedded in the semiconductor substrate. The capacitor includes first and second conductive stacks. The first conductive stack includes a first dummy gate strip disposed entirely within the STI region and a plurality of first metal dummy gate contacts landing on the first metal capacitor strip. The second conductive stack includes a second dummy gate strip disposed entirely within the STI region and extending in parallel with the first dummy gate strip, and a plurality of second dummy gate contacts landing on the second dummy gate strip, wherein the first conductive stack is electrically isolated from the second conductive stack.

    MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD
    6.
    发明申请
    MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD 有权

    公开(公告)号：US20210383048A1

    公开(公告)日：2021-12-09

    申请号：US17103159

    申请日：2020-11-24

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Chia-En HUANG ,  Chien-Ying CHEN

    IPC分类号： G06F30/392 ,  G06F30/398 ,  G03F1/70

    摘要： A memory device includes at least one bit line, at least one word line, and at least one memory cell comprising a capacitor and a transistor. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The insulating material is configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end.

    MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD
    8.
    发明申请
    MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD 有权

    公开(公告)号：US20230089590A1

    公开(公告)日：2023-03-23

    申请号：US18053030

    申请日：2022-11-07

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Meng-Sheng CHANG ,  Chia-En HUANG ,  Chien-Ying CHEN

    IPC分类号： G06F30/392 ,  G03F1/70 ,  G06F30/398

    摘要： A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.

    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING
    9.
    发明申请
    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING 有权

    公开(公告)号：US20230062566A1

    公开(公告)日：2023-03-02

    申请号：US17460206

    申请日：2021-08-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Meng-Sheng CHANG ,  Chia-En HUANG ,  Yi-Ching LIU ,  Yih WANG

    IPC分类号： G11C13/00

    摘要： Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.