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公开(公告)号：US20230385519A1
公开(公告)日：2023-11-30
申请号：US18362195
申请日：2023-07-31
发明人： Shao-Lun CHIEN , Pin-Dai SUE , Li-Chun TIEN , Ting-Wei CHIANG , Ting Yu CHEN
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G03F1/36
CPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G03F1/36
摘要： A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.
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公开(公告)号：US20210089702A1
公开(公告)日：2021-03-25
申请号：US17116745
申请日：2020-12-09
发明人： Shao-Lun CHIEN , Pin-Dai SUE , Li-Chun TIEN , Ting-Wei CHIANG , Ting Yu CHEN
IPC分类号： G06F30/398 , G03F1/36 , G06F30/392 , G06F30/394
摘要： A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.
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3.发明公开公开(公告)号：US20230260985A1
公开(公告)日：2023-08-17
申请号：US17843770
申请日：2022-06-17
发明人： Shun Li CHEN , Fei Fan DUAN , Ting Yu CHEN
IPC分类号： H01L27/02 , H01L27/118 , H01L21/8234
CPC分类号： H01L27/0207 , H01L27/11807 , H01L21/823437
摘要： A filler cell region (in a semiconductor device) includes: gate segments, a majority of first ends of which substantially align with a first reference line that parallel and proximal to a top boundary of the filler cell region, and a majority of second ends of which substantially align with a second reference line that is parallel and proximal to a bottom boundary of the filler cell region. First and second gate segments extend continuously across the filler cell region; and third & fourth and fifth & sixth gate segments are correspondingly coaxial and separated by corresponding gate-gaps. Relative to the first direction: a first end of the first gate segment extends to the top boundary of the filler cell region; and a second end of the second gate segment extends to the bottom boundary of the filler cell region.
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公开(公告)号：US20220188501A1
公开(公告)日：2022-06-16
申请号：US17689825
申请日：2022-03-08
发明人： Shao-Lun CHIEN , Pin-Dai SUE , Li-Chun TIEN , Ting-Wei CHIANG , Ting Yu CHEN
IPC分类号： G06F30/398 , G03F1/36 , G06F30/392 , G06F30/394
摘要： A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.
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公开(公告)号：US20220075923A1
公开(公告)日：2022-03-10
申请号：US17525375
申请日：2021-11-12
发明人： Li-Chun TIEN , Shun Li CHEN , Ting-Wei CHIANG , Ting Yu CHEN , XinYong WANG
IPC分类号： G06F30/394 , H01L23/522 , H01L23/528 , G06F30/30 , G06F30/392
摘要： A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h≥1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.
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6.发明申请公开(公告)号：US20180150586A1
公开(公告)日：2018-05-31
申请号：US15474460
申请日：2017-03-30
发明人： Li-Chun TIEN , Ting-Wei CHIANG , Shun Li CHEN , Ting Yu CHEN , XinYong WANG
IPC分类号： G06F17/50 , H01L23/528 , H01L23/522
CPC分类号： G06F17/5072 , G06F17/5045 , G06F17/5077 , G06F17/5081 , H01L21/76895 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/11807
摘要： A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.
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公开(公告)号：US20210326511A1
公开(公告)日：2021-10-21
申请号：US17362170
申请日：2021-06-29
发明人： Jian-Sing LI , Jung-Chan YANG , Ting Yu CHEN , Ting-Wei CHIANG
IPC分类号： G06F30/394 , G06F30/392
摘要： A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.
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8.发明申请公开(公告)号：US20210286928A1
公开(公告)日：2021-09-16
申请号：US17332819
申请日：2021-05-27
发明人： Li-Chun TIEN , Shun Li CHEN , Ting-Wei CHIANG , Ting Yu CHEN , XinYong WANG
IPC分类号： G06F30/392 , G06F30/30 , G06F30/394 , G06F30/398 , H01L27/118 , H01L23/528 , H01L23/522 , H01L27/02 , H01L21/768
摘要： A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.
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公开(公告)号：US20210056249A1
公开(公告)日：2021-02-25
申请号：US17081438
申请日：2020-10-27
发明人： Shun Li CHEN , Li-Chun TIEN , Ting Yu CHEN , Wei-Ling CHANG
IPC分类号： G06F30/398 , G03F1/36 , G06F30/392 , G06F30/394 , G06F30/3947 , G06F30/3953
摘要： A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.
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公开(公告)号：US20200082052A1
公开(公告)日：2020-03-12
申请号：US16530703
申请日：2019-08-02
发明人： Shao-Lun CHIEN , Ting-Wei CHIANG , Li-Chun TIEN , Pin-Dai SUE , Ting Yu CHEN
摘要： A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.
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