公开(公告)号：US20230023505A1

公开(公告)日：2023-01-26

申请号：US17692996

申请日：2022-03-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chieh LEE ,  Chia-En HUANG ,  Yi-Ching LIU ,  Wen-Chang CHENG ,  Yih WANG

IPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C5/06

摘要： A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

公开(公告)号：US20240331760A1

公开(公告)日：2024-10-03

申请号：US18743950

申请日：2024-06-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chieh LEE ,  Chia-En HUANG ,  Yi-Ching LIU ,  Wen-Chang CHENG ,  Yih WANG

IPC分类号： G11C11/4091 ,  G11C5/06 ,  G11C11/4094 ,  G11C11/4096 ,  H03K19/20

CPC分类号： G11C11/4091 ,  G11C5/063 ,  G11C11/4094 ,  G11C11/4096 ,  H03K19/20

摘要： A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.

公开(公告)号：US20230030605A1

公开(公告)日：2023-02-02

申请号：US17589729

申请日：2022-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chieh LEE ,  Chia-En HUANG ,  Yi-Ching LIU ,  Wen-Chang CHENG ,  Yih WANG

IPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C5/06 ,  H03K19/20

摘要： A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.