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公开(公告)号：US20230410887A1
公开(公告)日：2023-12-21
申请号：US18182696
申请日：2023-03-13
发明人： Chieh LEE , Chia-En Huang , Chun-Ying LEE , Yi-Ching LIU , Yih WANG , Rose Tseng , Yao-Jen Yang , Jonathan Tsung-Yung Chang
IPC分类号： G11C11/4091 , G11C5/06 , G11C11/408
CPC分类号： G11C11/4091 , G11C5/06 , G11C11/4085
摘要： A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.
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公开(公告)号：US20230062566A1
公开(公告)日：2023-03-02
申请号：US17460206
申请日：2021-08-28
发明人： Meng-Sheng CHANG , Chia-En HUANG , Yi-Ching LIU , Yih WANG
IPC分类号： G11C13/00
摘要： Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.
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公开(公告)号：US20240331771A1
公开(公告)日：2024-10-03
申请号：US18741201
申请日：2024-06-12
发明人： Meng-Sheng Chang , Chia-En HUANG , Yi-Ching LIU , Yih WANG
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/003
摘要： Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.
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公开(公告)号：US20240331760A1
公开(公告)日：2024-10-03
申请号：US18743950
申请日：2024-06-14
发明人： Chieh LEE , Chia-En HUANG , Yi-Ching LIU , Wen-Chang CHENG , Yih WANG
IPC分类号： G11C11/4091 , G11C5/06 , G11C11/4094 , G11C11/4096 , H03K19/20
CPC分类号： G11C11/4091 , G11C5/063 , G11C11/4094 , G11C11/4096 , H03K19/20
摘要： A memory circuit includes a boundary layer, a first circuit positioned on a first side of the boundary layer and including a DRAM array including a plurality of DRAM cells, a second circuit positioned on a second side of the boundary layer opposite the first side and including a computation circuit, the computation circuit including a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit. Each bit line of the plurality of bit lines includes a via structure positioned in the boundary layer and the plurality of DRAM cells of the first circuit positioned on the first side of the boundary layer is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.
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公开(公告)号：US20230238303A1
公开(公告)日：2023-07-27
申请号：US17583415
申请日：2022-01-25
发明人： Meng-Han LIN , Chia-En HUANG , Yi-Ching LIU
IPC分类号： H01L23/48 , H01L23/522 , H01L23/528 , H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565
CPC分类号： H01L23/481 , H01L23/5226 , H01L23/5283 , H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565
摘要： A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.
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公开(公告)号：US20220366951A1
公开(公告)日：2022-11-17
申请号：US17815121
申请日：2022-07-26
发明人： Yi-Ching LIU , Chia-En HUANG , Yih WANG
摘要： A method of operating a memory circuit includes enabling a first row of select transistors, disabling a second row of select transistors, enabling a first row of memory cells in response to a first word line signal, and disabling a second row of memory cells in response to a second word line signal. Enabling the first row of select transistors includes turning on a first select transistor in the first row of select transistors in response to a first select line signal thereby electrically coupling a first local bit line and a global bit line to each other. Disabling the second row of select transistors includes turning off a second select transistor in the second row of select transistors in response to a second select line signal thereby electrically decoupling a second local bit line and the global bit line from each other.
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公开(公告)号：US20240062818A1
公开(公告)日：2024-02-22
申请号：US17889707
申请日：2022-08-17
发明人： Chun-Ying LEE , Chieh LEE , Chia-En HUANG , Chi LO , Yi-Ching LIU
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/30
摘要： A memory device is provided, including a first word line driver configured to activate a first word line. The first word line driver includes a first transistor configured to operate in response to a first control signal having a first voltage level to transmit a first word line voltage to a first word line and a second transistor coupled between the first word line and a supply voltage terminal and configured to be turned off in response to a second control signal having a second voltage level different from the first voltage level.
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公开(公告)号：US20230066081A1
公开(公告)日：2023-03-02
申请号：US17460215
申请日：2021-08-28
发明人： Meng-Sheng Chang , Chia-En HUANG , Yi-Ching LIU , Yih Wang
IPC分类号： G11C5/06
摘要： Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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公开(公告)号：US20240071504A1
公开(公告)日：2024-02-29
申请号：US17898733
申请日：2022-08-30
发明人： Pei-Chun LIAO , Yu-Kai CHANG , Yi-Ching LIU , Yu-Ming LIN , Yih WANG , Chieh LEE
摘要： A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
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公开(公告)号：US20230262986A1
公开(公告)日：2023-08-17
申请号：US17669802
申请日：2022-02-11
发明人： Wen-Ling LU , Chia-En HUANG , Ya-Yun CHENG , Yi-Ching LIU , Huan-Sheng WEI , Chung-Wei WU
IPC分类号： H01L27/11597 , H01L27/11587 , G11C5/06
CPC分类号： H01L27/11597 , G11C5/063 , H01L27/11587
摘要： A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.
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