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公开(公告)号：US20240071442A1
公开(公告)日：2024-02-29
申请号：US17896506
申请日：2022-08-26
发明人： Min-Chiao YEH , Chieh LEE , Chia-En HUANG , Ji Kuan LEE , Yao-Jen YANG
CPC分类号： G11C7/12 , G11C13/0026 , G11C13/0028
摘要： A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.
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公开(公告)号：US20230343404A1
公开(公告)日：2023-10-26
申请号：US18345530
申请日：2023-06-30
发明人： Gu-Huan LI , Tung-Cheng CHANG , Perng-Fei YUH , Chia-En HUANG , Chun-Ying LEE LEE , Yih WANG
摘要： A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.
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公开(公告)号：US20230328998A1
公开(公告)日：2023-10-12
申请号：US17718071
申请日：2022-04-11
发明人： Meng-Han LIN , Chia-En HUANG
IPC分类号： H01L27/1159 , H01L27/11597 , H01L29/78 , H01L29/66 , H01L21/28 , H01L29/51
CPC分类号： H01L27/1159 , H01L27/11597 , H01L29/78391 , H01L29/6684 , H01L29/40111 , H01L29/516 , H01L29/7855 , H01L29/66795
摘要： A memory device comprises a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is over a substrate. The gate dielectric layer is on a sidewall of the word line. The semiconductor layer is on a sidewall of the gate dielectric layer. The source line is in contact with a first region of a sidewall of the semiconductor layer. The resistance-switchable element is in contact with a second region of the sidewall of the semiconductor layer.
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公开(公告)号：US20230292531A1
公开(公告)日：2023-09-14
申请号：US17690650
申请日：2022-03-09
发明人： Meng-Han LIN , Chia-En HUANG
IPC分类号： H01L27/24 , H01L27/11514 , H01L27/22
CPC分类号： H01L27/2454 , H01L27/11514 , H01L27/228
摘要： A memory device includes two word-line electrodes, two source-line electrodes, and two data storage features for use by four memory cells, which are referred to as first, second, third and fourth memory cells. One word-line electrode is common to the first and second memory cells, and the other word-line electrode is common to the third and fourth memory cells. One source-line electrode is common to the first and second memory cells, and the other source-line electrode is common to the third and fourth memory cells. One data storage feature is common to the first and third memory cells, and the other data storage feature is common to the second and fourth memory cells.
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公开(公告)号：US20230262986A1
公开(公告)日：2023-08-17
申请号：US17669802
申请日：2022-02-11
发明人： Wen-Ling LU , Chia-En HUANG , Ya-Yun CHENG , Yi-Ching LIU , Huan-Sheng WEI , Chung-Wei WU
IPC分类号： H01L27/11597 , H01L27/11587 , G11C5/06
CPC分类号： H01L27/11597 , G11C5/063 , H01L27/11587
摘要： A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.
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公开(公告)号：US20230240063A1
公开(公告)日：2023-07-27
申请号：US17584716
申请日：2022-01-26
发明人： Peng-Chun LIOU , Chia-En HUANG , Ya-Yun CHENG
IPC分类号： H01L27/108 , H01L29/10 , H01L29/417 , H01L29/24
CPC分类号： H01L27/10811 , H01L27/10855 , H01L29/1033 , H01L29/41775 , H01L29/24
摘要： A memory cell includes a transistor and a capacitor. The transistor includes a gate electrode, a gate dielectric disposed over the gate electrode, a channel feature disposed over the gate dielectric and overlapping the gate electrode, a source electrode disposed over the channel feature and electrically connected to the capacitor, and two drain electrodes disposed over the channel feature. The drain electrodes are disposed at opposite sides of the source electrode. The channel feature has a first channel portion extending between and interconnecting one drain electrode and the source electrode, and a second channel portion extending between and interconnecting the other drain electrode and the source electrode. The gate electrode overlaps both of the first channel portion and the second channel portion of the channel feature.
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公开(公告)号：US20230050710A1
公开(公告)日：2023-02-16
申请号：US17401907
申请日：2021-08-13
发明人： Gu-Huan LI , Tung-Cheng CHANG , Perng-Fei YUH , Chia-En HUANG , Chun-Ying LEE , Yih WANG
IPC分类号： G11C17/18 , H01L27/112 , G11C17/16
摘要： A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.
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公开(公告)号：US20230023505A1
公开(公告)日：2023-01-26
申请号：US17692996
申请日：2022-03-11
发明人： Chieh LEE , Chia-En HUANG , Yi-Ching LIU , Wen-Chang CHENG , Yih WANG
IPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C5/06
摘要： A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.
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公开(公告)号：US20220028439A1
公开(公告)日：2022-01-27
申请号：US17154514
申请日：2021-01-21
发明人： Yi-Ching LIU , Chia-En HUANG , Yih WANG
摘要： A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, a first bit line, a second bit line and a first source line. The first bit lines extends in a first direction, and is coupled to the first memory cell, the second memory cell and the first select transistor. The second bit line extends in the first direction, and is coupled to the first select transistor. The first source line extends in the first direction, is coupled to the first memory cell and the second memory cell, and is separated from the first bit line in a second direction different from the first direction.
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公开(公告)号：US20210376154A1
公开(公告)日：2021-12-02
申请号：US17185549
申请日：2021-02-25
发明人： Meng-Han LIN , Chia-En HUANG , Han-Jong CHIA , Martin LIU , Sai-Hooi YEONG , Yih WANG
IPC分类号： H01L29/78 , G11C11/22 , H01L27/1159 , H01L29/66
摘要： A ferroelectric field-effect transistor (FeFET) configured as a multi-bit storage device, the FeFET including: a semiconductor substrate that has a source region in the semiconductor substrate, and a drain region in the semiconductor substrate; a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack, the gate stack including a ferroelectric layer over the semiconductor substrate, and a gate region over the ferroelectric layer. The transistor also includes first and second ends of the ferroelectric layer which are proximal correspondingly to the source and drain regions. The ferroelectric layer includes dipoles. A first set of dipoles at the first end of the ferroelectric layer has a first polarization. A second set of dipoles at the second end of the ferroelectric layer has a second polarization, the second polarization being substantially opposite of the first polarization.
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