公开(公告)号：US12080372B2

公开(公告)日：2024-09-03

申请号：US18064048

申请日：2022-12-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

发明人： He-Zhou Wan ,  Xiuli Yang ,  Ming-En Bu ,  Mengxiang Xu ,  Zong-Liang Cao

IPC分类号： G11C5/14

CPC分类号： G11C5/148

摘要： A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.

公开(公告)号：US09646663B2

公开(公告)日：2017-05-09

申请号：US14751820

申请日：2015-06-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ming-En Bu ,  Xiuli Yang ,  He-Zhou Wan ,  Mu-Jen Huang ,  Jie Cai

IPC分类号： G11C8/18 ,  G11C8/16 ,  G11C7/10 ,  G11C8/12

CPC分类号： G11C8/16 ,  G11C7/1075 ,  G11C8/12 ,  G11C8/18

摘要： In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.

公开(公告)号：US09490006B2

公开(公告)日：2016-11-08

申请号：US14622063

申请日：2015-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Xiuli Yang ,  He-Zhou Wan ,  Ming-En Bu ,  Mu-Jen Huang ,  Ching-Wei Wu

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00 ,  G11C11/418 ,  H04J3/06 ,  G11C11/419

CPC分类号： G11C11/418 ,  G11C7/1075 ,  G11C11/419 ,  H04J3/0644

摘要： In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.

摘要翻译： 在一些实施例中，时分复用（TDM）电路被配置为接收外部时钟信号并产生在外部时钟信号的时钟周期期间具有至少一个脉冲的内部时钟信号。 地址选择器被配置为在所述至少一个脉冲之一内的第一次之前选择当前地址，并且从第一次开始选择下一个地址以生成所选择的地址。 地址存储元件被配置为从地址选择器接收所选择的地址并提供通过或存储的地址。 所提供的地址是基本上遍及至少一个脉冲中的一个的当前地址。 单端口（SP）存储器被配置为响应于内部时钟信号来访问由地址存储元件提供的地址处的至少一个SP存储器单元。

公开(公告)号：US09245615B2

公开(公告)日：2016-01-26

申请号：US14220025

申请日：2014-03-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ching-Wei Wu ,  He-Zhou Wan ,  Ming-En Bu ,  Xiuli Yang ,  Cheng Hung Lee ,  Mu-Jen Huang

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G11C8/16

摘要： A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.

摘要翻译： 双端口SRAM的升压系统包括比较器和升压电路。 比较器被配置为比较第一端口的第一行地址和第二端口的第二行地址，并输出第一使能信号。 升压电路被配置为根据第一使能信号来升高第一电压源和第二电压源之间的电压差。