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1.发明授权公开(公告)号：US11107530B2
公开(公告)日：2021-08-31
申请号：US16732219
申请日：2019-12-31
Inventor： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC: G11C11/00 , G11C14/00 , G11C11/419 , G11C11/16
Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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公开(公告)号：US09711190B2
公开(公告)日：2017-07-18
申请号：US14249428
申请日：2014-04-10
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
CPC classification number: G11C5/147 , G11C7/062 , G11C7/08 , G11C2207/063
Abstract: A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.
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3.发明申请公开(公告)号：US20210201997A1
公开(公告)日：2021-07-01
申请号：US16732219
申请日：2019-12-31
Inventor： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC: G11C14/00 , G11C11/419 , G11C11/16
Abstract: Disclosed herein are related to an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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Patent Agency Ranking
公开(公告)号：US09910451B2
公开(公告)日：2018-03-06
申请号：US14181848
申请日：2014-02-17
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
CPC classification number: G05F1/575 , G05F1/461 , G05F1/563 , H02M3/07 , H02M2001/0045
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
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公开(公告)号：US20150234403A1
公开(公告)日：2015-08-20
申请号：US14181848
申请日：2014-02-17
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
IPC: G05F1/575
CPC classification number: G05F1/575 , G05F1/461 , G05F1/563 , H02M3/07 , H02M2001/0045
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
Abstract translation: 提供了一个低压降（LDO）调节器。 LDO调节器包括作为闭环控制系统操作的第一电路。 第一电路被配置为控制第一节点处的电压，使得第一节点处的电压基本上等于指定的调节器输出电压。 LDO调节器包括作为开环控制系统操作的第二电路。 第二电路被配置为当流过负载的电流从第一电流改变到第二电流时，增加第一节点处的电压。 第一电流基本上等于0安培。
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公开(公告)号：US10281942B2
公开(公告)日：2019-05-07
申请号：US15904536
申请日：2018-02-26
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
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公开(公告)号：US20180188756A1
公开(公告)日：2018-07-05
申请号：US15904536
申请日：2018-02-26
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
CPC classification number: G05F1/575 , G05F1/461 , G05F1/563 , H02M3/07 , H02M2001/0045
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
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公开(公告)号：US20150294696A1
公开(公告)日：2015-10-15
申请号：US14249428
申请日：2014-04-10
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
CPC classification number: G11C5/147 , G11C7/062 , G11C7/08 , G11C2207/063
Abstract: A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.
Abstract translation: 提供了连接到偏置电压的稳定电路。 稳定电路被配置为禁止由通过第一寄生电容连接到偏置电压的一个或多个节点的电压的第一变化引起的偏置电压的电压变化。 在一些实施例中，稳定电路通过在电压的第一次变化期间从第一电压电平变化到第二电压电平的第二寄生电容来引起偏置电压上的电压，使得在第一电压电平下引起的寄生电压的总变化 在第一次电压变化期间的偏置电压接近0 V.
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