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公开(公告)号：US09711190B2
公开(公告)日：2017-07-18
申请号：US14249428
申请日：2014-04-10
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
CPC classification number: G11C5/147 , G11C7/062 , G11C7/08 , G11C2207/063
Abstract: A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.
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公开(公告)号：US09910451B2
公开(公告)日：2018-03-06
申请号：US14181848
申请日：2014-02-17
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
CPC classification number: G05F1/575 , G05F1/461 , G05F1/563 , H02M3/07 , H02M2001/0045
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
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公开(公告)号：US09742497B2
公开(公告)日：2017-08-22
申请号：US15230646
申请日：2016-08-08
Inventor： Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih , Ying-Hao Kuo
IPC: H04B10/00 , H04B10/43 , H01S5/30 , H01S5/02 , H01S5/026 , G02B6/12 , G02B6/122 , G02B6/34 , G02F1/025 , H01L21/306 , H01L23/31 , H01L27/06 , H01L29/08 , H01L29/66 , H01L31/112 , H01S5/183 , H01S5/028 , G02F1/015
CPC classification number: H04B10/43 , G02B6/12002 , G02B6/12004 , G02B6/1226 , G02B6/34 , G02F1/025 , G02F2001/0157 , H01L21/30604 , H01L23/3171 , H01L27/0688 , H01L29/0847 , H01L29/66477 , H01L31/112 , H01S5/021 , H01S5/026 , H01S5/0261 , H01S5/0265 , H01S5/0285 , H01S5/183 , H01S5/18302 , H01S5/18361 , H01S5/3027
Abstract: A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.
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公开(公告)号：US20160359566A1
公开(公告)日：2016-12-08
申请号：US15230646
申请日：2016-08-08
Inventor： Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih , Ying-Hao Kuo
IPC: H04B10/43 , H01L29/08 , H01L27/06 , H01L29/66 , H01L21/306 , G02F1/025 , H01S5/183 , H01L31/112 , G02B6/12 , G02B6/34 , G02B6/122 , H01L23/31 , H01S5/026
CPC classification number: H04B10/43 , G02B6/12002 , G02B6/12004 , G02B6/1226 , G02B6/34 , G02F1/025 , G02F2001/0157 , H01L21/30604 , H01L23/3171 , H01L27/0688 , H01L29/0847 , H01L29/66477 , H01L31/112 , H01S5/021 , H01S5/026 , H01S5/0261 , H01S5/0265 , H01S5/0285 , H01S5/183 , H01S5/18302 , H01S5/18361 , H01S5/3027
Abstract: A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.
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公开(公告)号：US09413140B2
公开(公告)日：2016-08-09
申请号：US14133699
申请日：2013-12-19
Inventor： Hung-Chang Yu , Ying-Hao Kuo , Kai-Chun Lin , Yue-Der Chih
CPC classification number: H04B10/43 , G02B6/12002 , G02B6/12004 , G02B6/1226 , G02B6/34 , G02F1/025 , G02F2001/0157 , H01L21/30604 , H01L23/3171 , H01L27/0688 , H01L29/0847 , H01L29/66477 , H01L31/112 , H01S5/021 , H01S5/026 , H01S5/0261 , H01S5/0265 , H01S5/0285 , H01S5/183 , H01S5/18302 , H01S5/18361 , H01S5/3027
Abstract: A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.
Abstract translation: 对半导体装置及其形成方法进行说明。 半导体装置包括包括第一光收发器的第一层和包括第二光收发器的第二层。 第一个串行器/解串器（SerDes）连接到第一个光收发器，第二个SerDes连接到第二个光收发器。 SerDes将并行数据输入转换为串行数据输出，包括第一个收发器向第二个收发器发送的时钟信号。 半导体布置具有比不使用光学器件对准的传统层内通信布置更低的面积损失，并且减轻与常规技术相关联的对准问题。
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Patent Agency Ranking
公开(公告)号：US20150294696A1
公开(公告)日：2015-10-15
申请号：US14249428
申请日：2014-04-10
Inventor： Kai-Chun Lin , Hung-Chang Yu , Ku-Feng Lin , Yue-Der Chih
CPC classification number: G11C5/147 , G11C7/062 , G11C7/08 , G11C2207/063
Abstract: A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V.
Abstract translation: 提供了连接到偏置电压的稳定电路。 稳定电路被配置为禁止由通过第一寄生电容连接到偏置电压的一个或多个节点的电压的第一变化引起的偏置电压的电压变化。 在一些实施例中，稳定电路通过在电压的第一次变化期间从第一电压电平变化到第二电压电平的第二寄生电容来引起偏置电压上的电压，使得在第一电压电平下引起的寄生电压的总变化 在第一次电压变化期间的偏置电压接近0 V.
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公开(公告)号：US10281942B2
公开(公告)日：2019-05-07
申请号：US15904536
申请日：2018-02-26
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
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公开(公告)号：US20180188756A1
公开(公告)日：2018-07-05
申请号：US15904536
申请日：2018-02-26
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
CPC classification number: G05F1/575 , G05F1/461 , G05F1/563 , H02M3/07 , H02M2001/0045
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
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公开(公告)号：US20150180210A1
公开(公告)日：2015-06-25
申请号：US14133699
申请日：2013-12-19
Inventor： Hung-Chang Yu , Ying-Hao Kuo , Kai-Chun Lin , Yue-Der Chih
CPC classification number: H04B10/43 , G02B6/12002 , G02B6/12004 , G02B6/1226 , G02B6/34 , G02F1/025 , G02F2001/0157 , H01L21/30604 , H01L23/3171 , H01L27/0688 , H01L29/0847 , H01L29/66477 , H01L31/112 , H01S5/021 , H01S5/026 , H01S5/0261 , H01S5/0265 , H01S5/0285 , H01S5/183 , H01S5/18302 , H01S5/18361 , H01S5/3027
Abstract: A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.
Abstract translation: 对半导体装置及其形成方法进行说明。 半导体装置包括包括第一光收发器的第一层和包括第二光收发器的第二层。 第一个串行器/解串器（SerDes）连接到第一个光收发器，第二个SerDes连接到第二个光收发器。 SerDes将并行数据输入转换为串行数据输出，包括第一个收发器向第二个收发器发送的时钟信号。 半导体布置具有比不使用光学器件对准的传统层内通信布置更低的面积损失，并且减轻与常规技术相关联的对准问题。
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公开(公告)号：US20150234403A1
公开(公告)日：2015-08-20
申请号：US14181848
申请日：2014-02-17
Inventor： Yuan-Long Siao , Ku-Feng Lin , Kai-Chun Lin , Hung-Chang Yu , Chia-Fu Lee , Yue-Der Chih
IPC: G05F1/575
CPC classification number: G05F1/575 , G05F1/461 , G05F1/563 , H02M3/07 , H02M2001/0045
Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.
Abstract translation: 提供了一个低压降（LDO）调节器。 LDO调节器包括作为闭环控制系统操作的第一电路。 第一电路被配置为控制第一节点处的电压，使得第一节点处的电压基本上等于指定的调节器输出电压。 LDO调节器包括作为开环控制系统操作的第二电路。 第二电路被配置为当流过负载的电流从第一电流改变到第二电流时，增加第一节点处的电压。 第一电流基本上等于0安培。
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