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    RRAM and method of read operation for RRAM
    1.
    发明授权
    RRAM and method of read operation for RRAM 有权
    RRAM和RRAM读操作方法

    公开(公告)号：US09576651B2

    公开(公告)日：2017-02-21

    申请号：US14601458

    申请日：2015-01-21

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang ,  Chia-Fu Lee

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/52 ,  G11C2213/79

    Abstract: According to one embodiment, a method of RRAM operations is provided. The method includes the following operations: providing a first voltage difference across a resistor of the RRAM during a read operation; and providing a second voltage difference across the resistor of the RRAM during a reset operation, wherein the first voltage difference has the same polarity as the second voltage difference.

    Abstract translation: 根据一个实施例，提供了一种RRAM操作的方法。 该方法包括以下操作：在读操作期间在RRAM的电阻器两端提供第一电压差; 以及在复位操作期间在所述RRAM的电阻器两端提供第二电压差，其中所述第一电压差具有与所述第二电压差相同的极性。

    LOW-DROPOUT REGULATOR
    2.
    发明申请
    LOW-DROPOUT REGULATOR 有权
    低压差稳压器

    公开(公告)号：US20150234403A1

    公开(公告)日：2015-08-20

    申请号：US14181848

    申请日：2014-02-17

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Yuan-Long Siao ,  Ku-Feng Lin ,  Kai-Chun Lin ,  Hung-Chang Yu ,  Chia-Fu Lee ,  Yue-Der Chih

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/461 ,  G05F1/563 ,  H02M3/07 ,  H02M2001/0045

    Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.

    Abstract translation: 提供了一个低压降（LDO）调节器。 LDO调节器包括作为闭环控制系统操作的第一电路。 第一电路被配置为控制第一节点处的电压，使得第一节点处的电压基本上等于指定的调节器输出电压。 LDO调节器包括作为开环控制系统操作的第二电路。 第二电路被配置为当流过负载的电流从第一电流改变到第二电流时，增加第一节点处的电压。 第一电流基本上等于0安培。

    Duo-level word line driver
    3.
    发明授权
    Duo-level word line driver 有权

    公开(公告)号：US11264093B1

    公开(公告)日：2022-03-01

    申请号：US17002443

    申请日：2020-08-25

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Po-Hao Lee ,  Chia-Fu Lee ,  Yi-Chun Shih

    IPC: G11C7/12 ,  G11C11/00 ,  G11C13/00

    Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.

    Memory repair scheme
    4.
    发明授权
    Memory repair scheme 有权

    公开(公告)号：US11211142B2

    公开(公告)日：2021-12-28

    申请号：US16829149

    申请日：2020-03-25

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Yi-Chun Shih ,  Po-Hao Lee ,  Chia-Fu Lee ,  Yu-Der Chih ,  Yu-Lin Chen

    IPC: G11C16/06 ,  G11C29/00 ,  G11C29/44 ,  G06F12/02

    Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

    Memory Repair Scheme
    5.
    发明申请
    Memory Repair Scheme 审中-公开

    公开(公告)号：US20190035487A1

    公开(公告)日：2019-01-31

    申请号：US16044621

    申请日：2018-07-25

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Yi-Chun Shih ,  Po-Hao Lee ,  Chia-Fu Lee ,  Yu-Der Chih ,  Yu-Lin Chen

    IPC: G11C29/00 ,  G11C29/44 ,  G06F12/02

    Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

    On-chip power regulation system for MRAM operation
    7.
    发明授权
    On-chip power regulation system for MRAM operation 有权

    公开(公告)号：US11137785B2

    公开(公告)日：2021-10-05

    申请号：US16787506

    申请日：2020-02-11

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Yen-An Chang ,  Chieh-Pu Lo ,  Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

    IPC: G05F1/575 ,  G11C11/16

    Abstract: In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.

    Memory Repair Scheme
    8.
    发明申请
    Memory Repair Scheme 审中-公开

    公开(公告)号：US20200227133A1

    公开(公告)日：2020-07-16

    申请号：US16829149

    申请日：2020-03-25

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Yi-Chun Shih ,  Po-Hao Lee ,  Chia-Fu Lee ,  Yu-Der Chih ,  Yu-Lin Chen

    IPC: G11C29/00 ,  G11C29/44 ,  G06F12/02

    Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.

    Memory device with a low-current reference circuit
    9.
    发明授权
    Memory device with a low-current reference circuit 有权

    公开(公告)号：US10319423B2

    公开(公告)日：2019-06-11

    申请号：US15800700

    申请日：2017-11-01

    Applicant: Taiwan Semiconductor Manufacturing Company Limited

    Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

    IPC: G11C11/16 ,  G11C7/06 ,  G11C11/15 ,  H01L43/02 ,  G11C7/14

    Abstract: A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is configured to generate a reference current and includes a plurality of magnetic resistive elements. At least one of the magnetic resistive elements is in a high resistance state. The sense amplifier is coupled to the memory cell unit and the reference circuit and is configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell, to amplify a level of the sensed bit of data, and to output the amplified bit of data.

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