公开(公告)号：US11842920B2

公开(公告)日：2023-12-12

申请号：US17353618

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66477

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

公开(公告)号：US11075107B2

公开(公告)日：2021-07-27

申请号：US16371900

申请日：2019-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

公开(公告)号：US11936299B2

公开(公告)日：2024-03-19

申请号：US17027032

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chu Fu Chen ,  Chi-Feng Huang ,  Chia-Chung Chen ,  Chin-Lung Chen ,  Victor Chiang Liang ,  Chia-Cheng Pao

IPC: H02M3/158 ,  H01L21/84 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/80 ,  H01L21/265

CPC classification number: H02M3/1582 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/80 ,  H01L21/26586 ,  H02M3/158

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

公开(公告)号：US10784781B2

公开(公告)日：2020-09-22

申请号：US15938482

申请日：2018-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chu Fu Chen ,  Chi-Feng Huang ,  Chia-Chung Chen ,  Chin-Lung Chen ,  Victor Chiang Liang ,  Chia-Cheng Pao

IPC: H02M3/158 ,  H01L29/78 ,  H01L29/423 ,  H01L21/84 ,  H01L29/80 ,  H01L29/08 ,  H01L29/66

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.