公开(公告)号：US11121028B2

公开(公告)日：2021-09-14

申请号：US16570325

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Ling-Fu Nieh ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Ting-Hsun Chang ,  Chia-Wei Ho ,  Liang-Guang Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.

公开(公告)号：US10741665B2

公开(公告)日：2020-08-11

申请号：US16101065

申请日：2018-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778 ,  H01L29/10 ,  H01L29/267 ,  H01L21/02

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US20200006125A1

公开(公告)日：2020-01-02

申请号：US16570325

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.,

Inventor： Chun-Wei Hsu ,  Ling-Fu Nieh ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Yi-Sheng Lin ,  Ting-Hsun Chang ,  Chia-Wei Ho ,  Liang-Guang Chen

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.

公开(公告)号：US09871030B2

公开(公告)日：2018-01-16

申请号：US15357308

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： King-Yuen Wong ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8258 ,  H01L23/522 ,  H01L29/205 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/30612 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

公开(公告)号：US20170317184A1

公开(公告)日：2017-11-02

申请号：US15645463

申请日：2017-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry YU ,  Fu-Wei YAO ,  Chen-Ju YU ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/02 ,  H01L29/267 ,  H01L29/20 ,  H01L29/417 ,  H01L29/43

CPC classification number: H01L29/66462 ,  H01L21/02271 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L2924/0002

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

公开(公告)号：US09224829B2

公开(公告)日：2015-12-29

申请号：US14267954

申请日：2014-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： King-Yuen Wong ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen ,  Chun-Wei Hsu

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L27/146 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L27/14689 ,  H01L29/1033 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42364 ,  H01L29/7787

Abstract: A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.

Abstract translation: 一种形成半导体结构的方法，所述方法包括在第一III-V化合物层上外延生长第二III-V化合物层。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 该方法还包括在第二III-V化合物层上形成源特征和漏极特征，在第二III-V化合物层上形成第三III-V化合物层，在第二III -V化合物层和第三III-V化合物层的顶表面，用氟处理第二III-V化合物层的部分上的栅极电介质层，并在处理的栅极电介质层上在源特征 和排水功能。

公开(公告)号：US11842920B2

公开(公告)日：2023-12-12

申请号：US17353618

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66477

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

公开(公告)号：US11075107B2

公开(公告)日：2021-07-27

申请号：US16371900

申请日：2019-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

公开(公告)号：US10283599B2

公开(公告)日：2019-05-07

申请号：US15670135

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei Yao ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chih-Wen Hsiung ,  King-Yuen Wong

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

公开(公告)号：US10164047B2

公开(公告)日：2018-12-25

申请号：US15443861

申请日：2017-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  King-Yuen Wong ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/10 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/201 ,  H01L29/205 ,  H01L29/06 ,  H01L29/08

Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.