公开(公告)号：US09824729B2

公开(公告)日：2017-11-21

申请号：US15434541

申请日：2017-02-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Cheng Hung Lee ,  Chiting Cheng ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Pankaj Aggarwal ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C11/419

摘要： A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.

公开(公告)号：US11651804B2

公开(公告)日：2023-05-16

申请号：US17335866

申请日：2021-06-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Chiting Cheng ,  Pankaj Aggarwal ,  Yen-Huei Chen ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C11/419

摘要： A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first memory cell array includes rows of memory cells and columns of memory cells. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line coupled to the first and second set of memory cells. The first set of pull-down cells or loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and configured to charge the first tracking bit line to a pre-charge voltage level responsive to a tracking enable signal.

公开(公告)号：US11031055B2

公开(公告)日：2021-06-08

申请号：US16783915

申请日：2020-02-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Cheng Hung Lee ,  Chiting Cheng ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Pankaj Aggarwal ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419

摘要： A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.

公开(公告)号：US10559333B2

公开(公告)日：2020-02-11

申请号：US16404463

申请日：2019-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Cheng Hung Lee ,  Chiting Cheng ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Pankaj Aggarwal ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419

摘要： A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.

公开(公告)号：US10319421B2

公开(公告)日：2019-06-11

申请号：US16005121

申请日：2018-06-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Cheng Hung Lee ,  Chiting Cheng ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Pankaj Aggarwal ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22 ,  G11C11/419

摘要： A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.

公开(公告)号：US09997219B2

公开(公告)日：2018-06-12

申请号：US15798710

申请日：2017-10-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Kuo Su ,  Cheng Hung Lee ,  Chiting Cheng ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Pankaj Aggarwal ,  Jhon Jhy Liaw

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C11/419

摘要： A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.

公开(公告)号：US09263123B2

公开(公告)日：2016-02-16

申请号：US14068771

申请日：2013-10-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chiting Cheng ,  Chien-Kuo Su ,  Cheng Hung Lee ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  H01L27/11 ,  G11C5/14 ,  G11C16/30 ,  G11C7/02 ,  G11C8/08 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C5/14 ,  G11C7/02 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418 ,  G11C16/30 ,  H01L27/11

摘要： A semiconductor memory device comprises an array of memory cells arranged in rows and columns, control lines coupled to the rows of memory cells for accessing the memory cells, conductive lines coupled to the rows of memory cells for powering the memory cells, and a control circuit configured to maintain non-selected conductive lines at a first voltage level and boost a selected conductive line to a second voltage level in an access operation, the second voltage level being higher than the first voltage level.

摘要翻译： 半导体存储器件包括排列成行和列的存储器单元的阵列，耦合到用于存取存储器单元的存储器单元行的控制线，耦合到用于为存储单元供电的存储单元行的导线;以及控制电路 被配置为将未选择的导线保持在第一电压电平，并且在访问操作中将所选导线升高到第二电压电平，所述第二电压电平高于所述第一电压电平。