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40 条记录 (耗时 0.029 秒)

    Power detection circuit
    3.
    发明授权
    Power detection circuit 有权

    公开(公告)号：US11598794B2

    公开(公告)日：2023-03-07

    申请号：US16935608

    申请日：2020-07-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chia-Chen Kuo ,  Chiting Cheng ,  Wei-jer Hsieh ,  Yangsyu Lin

    IPC分类号： H02H9/00 ,  G01R19/165 ,  H02H1/00 ,  H02H9/02

    摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.

    Bit line secondary drive circuit and method
    5.
    发明授权
    Bit line secondary drive circuit and method 有权

    公开(公告)号：US11562779B2

    公开(公告)日：2023-01-24

    申请号：US17109964

    申请日：2020-12-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Shang-Chi Wu ,  Yangsyu Lin ,  Chiting Cheng ,  Jonathan Tsung-Yung Chang ,  Mahmut Sinangil

    IPC分类号： G11C7/12 ,  G11C11/413 ,  G11C11/4094 ,  G11C11/412 ,  G11C11/4074 ,  G11C11/419

    摘要： A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.

    Clock circuit and method of operating the same
    6.
    发明授权
    Clock circuit and method of operating the same 有权

    公开(公告)号：US10951200B2

    公开(公告)日：2021-03-16

    申请号：US16800981

    申请日：2020-02-25

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Yangsyu Lin

    IPC分类号： H03K3/037 ,  G11C11/412 ,  G06F1/04 ,  G11C7/22 ,  G11C11/417

    摘要： A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

    MEMORY DEVICE WITH FLY WORD LINE
    7.
    发明申请
    MEMORY DEVICE WITH FLY WORD LINE 审中-公开

    公开(公告)号：US20190311765A1

    公开(公告)日：2019-10-10

    申请号：US16285811

    申请日：2019-02-26

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yangsyu Lin ,  Chiting Cheng

    IPC分类号： G11C11/418 ,  G11C11/419 ,  G11C5/02

    摘要： A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.

    Clock generating circuit and method of operating the same
    8.
    发明授权
    Clock generating circuit and method of operating the same 有权

    公开(公告)号：US10340897B2

    公开(公告)日：2019-07-02

    申请号：US16039824

    申请日：2018-07-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Yangsyu Lin

    IPC分类号： H03K3/037 ,  G11C11/412

    摘要： A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.

    Memory unit and method of testing the same
    10.
    发明授权
    Memory unit and method of testing the same 有权
    内存单元和测试方法相同

    公开(公告)号：US09324453B2

    公开(公告)日：2016-04-26

    申请号：US14222018

    申请日：2014-03-21

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Wei-Jer Hsieh ,  Hong-Chen Cheng ,  Chiting Cheng ,  Yangsyu Lin ,  Cheng Hung Lee ,  Jonathan Tsung-Yung Chang

    IPC分类号： G11C11/00 ,  G11C29/32 ,  G11C11/41

    CPC分类号： G11C29/32 ,  G11C11/41

    摘要： A memory unit that includes a tracking unit, a scan chain and a scan chain control unit. The tracking unit includes a tracking bit line, wherein the tracking unit is configured to receive a tracking control signal, selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal and generate a sense amplifier signal. The scan chain includes one or more logic devices, wherein the scan chain is configured to receive at least a first control signal. The scan chain control unit is connected to the scan chain and the tracking unit. The scan chain control unit is configured to receive the sense amplifier signal and generate the first scan chain control signal.

    摘要翻译： 一种存储器单元，包括跟踪单元，扫描链和扫描链控制单元。 跟踪单元包括跟踪位线，其中跟踪单元被配置为接收跟踪控制信号，响应于跟踪控制信号选择性地对跟踪位线上的电压进行充电或放电，并产生读出放大器信号。 扫描链包括一个或多个逻辑设备，其中扫描链被配置为接收至少第一控制信号。 扫描链控制单元连接到扫描链和跟踪单元。 扫描链控制单元被配置为接收读出放大器信号并产生第一扫描链控制信号。