公开(公告)号：US20150235954A1

公开(公告)日：2015-08-20

申请号：US14181493

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chung Chang ,  Jung-Chih Tsao ,  Chun Che ,  Yu-Ming Huang ,  Tain-Shang Chang ,  Jian-Shin Tsai

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.

Abstract translation: 一种用于形成多层屏障的方法包括在衬底上形成导电线，在导电线上沉积电介质层，在电介质层中形成插塞开口，通过多个沉积工艺和相应的等离子体处理工艺形成多层势垒。

公开(公告)号：US11177172B2

公开(公告)日：2021-11-16

申请号：US16685948

申请日：2019-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yan-Ming Tsai ,  Wei-Yip Loh ,  Yu-Ming Huang ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a source/drain structure disposed in the substrate at two sides of the gate structure, and a conductive plug. The source/drain structure includes an epitaxial layer and a dual metal silicide on the epitaxial layer. The epitaxial layer includes a first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. The dual metal silicide includes the first semiconductor material, the second semiconductor material, a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The conductive plug penetrates the dual metal silicide.

公开(公告)号：US10483164B2

公开(公告)日：2019-11-19

申请号：US15881159

申请日：2018-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yan-Ming Tsai ,  Wei-Yip Loh ,  Yu-Ming Huang ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor includes following steps. An epitaxial structure including a first semiconductor material and a second semiconductor material is provided. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. A metal-containing layer is deposited on the epitaxial structure. The metal containing layer includes a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The metal-containing layer and the epitaxial structure are annealed to form a metal silicide layer on the epitaxial structure. The metal silicide layer includes the first semiconductor material, the second semiconductor material, the first metal material, and the second metal material.

公开(公告)号：US09847296B2

公开(公告)日：2017-12-19

申请号：US14181493

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chung Chang ,  Jung-Chih Tsao ,  Chun Che Lin ,  Yu-Ming Huang ,  Tain-Shang Chang ,  Jian-Shin Tsai

IPC: H01L21/44 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.