公开(公告)号：US10998415B2

公开(公告)日：2021-05-04

申请号：US16692053

申请日：2019-11-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shiu-Ko JangJian ,  Chi-Wen Liu ,  Chih-Nan Wu ,  Chun Che Lin

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165

摘要： Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.

公开(公告)号：US20200236768A1

公开(公告)日：2020-07-23

申请号：US16839526

申请日：2020-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Wu ,  Tzung-Chi Fu ,  Chun Che Lin ,  Po-Chung Cheng ,  Huai-Tei Yang

IPC分类号： H05G2/00

摘要： An extreme ultra-violet (EUV) lithography system includes an EUV source and EUV scanner. A droplet generator provides a droplet stream in the EUV source. A gas shield is configured to surround the droplet stream. When a laser reacts a droplet in the stream EUV radiation and ionized particles are produced. The gas shield can reduce contamination resulting from the ionized particles by conveying the ionized particles to a droplet catcher. Components of the EUV source may be biased with a voltage to repel or attract ionized particles to reduce contamination from the ionized particles.

公开(公告)号：US09978793B2

公开(公告)日：2018-05-22

申请号：US14547958

申请日：2014-11-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shiu-Ko JangJian ,  Chin-Nan Wu ,  Chun Che Lin

IPC分类号： H01L27/146

CPC分类号： H01L27/14623 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

摘要： A method comprises implanting ions in a substrate to form a plurality of photo diodes, forming an interconnect layer over a first side of the substrate and applying a first halogen treatment process to a second side of the substrate and forming a first silicon-halogen compound layer over the second side of the substrate as a result of applying the first halogen treatment process.

公开(公告)号：US10090242B2

公开(公告)日：2018-10-02

申请号：US15244961

申请日：2016-08-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shiu-Ko JangJian ,  Tsung-Hsuan Hong ,  Chun Che Lin ,  Chih-Nan Wu

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

摘要： An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

公开(公告)号：US09847296B2

公开(公告)日：2017-12-19

申请号：US14181493

申请日：2014-02-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chung Chang ,  Jung-Chih Tsao ,  Chun Che Lin ,  Yu-Ming Huang ,  Tain-Shang Chang ,  Jian-Shin Tsai

IPC分类号： H01L21/44 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.

公开(公告)号：US20170033222A1

公开(公告)日：2017-02-02

申请号：US15290509

申请日：2016-10-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Nan WU ,  Shiu-Ko JangJian ,  Chun Che Lin ,  Wen-Cheng Hsuku

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

摘要： An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

摘要翻译： 提供了用于半导体器件的改进的导电特征和用于形成该特征的技术。 在示例性实施例中，半导体器件包括其上形成有栅极结构的衬底。 栅极结构包括设置在基板上的栅极电介质层，设置在栅极结构的侧表面上的生长控制材料和设置在生长控制材料上的栅电极填充材料。 栅极电极填充材料也设置在栅极结构的没有生长控制材料的底表面上。 在一些这样的实施例中，栅电极填充材料接触组成不同的第一表面和第二表面。

公开(公告)号：US09466494B2

公开(公告)日：2016-10-11

申请号：US14588223

申请日：2014-12-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Nan Wu ,  Shiu-Ko JangJian ,  Chun Che Lin ,  Wen-Cheng HsuKu

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7851 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

摘要： An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

摘要翻译： 提供了用于半导体器件的改进的导电特征和用于形成该特征的技术。 在示例性实施例中，半导体器件包括其上形成有栅极结构的衬底。 栅极结构包括设置在基板上的栅极电介质层，设置在栅极结构的侧表面上的生长控制材料和设置在生长控制材料上的栅电极填充材料。 栅极电极填充材料也设置在栅极结构的没有生长控制材料的底表面上。 在一些这样的实施例中，栅电极填充材料接触组成不同的第一表面和第二表面。

公开(公告)号：US20160111325A1

公开(公告)日：2016-04-21

申请号：US14689929

申请日：2015-04-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shiu-Ko JangJian ,  Tsung-Hsuan Hong ,  Chun Che Lin ,  Chih-Nan Wu

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

摘要翻译： 集成电路结构包括介电层和蚀刻停止层。 蚀刻停止层包括在第一介电层上包括金属氮化物的第一子层，以及覆盖或位于第一子层下面的第二子层。 第二子层包括包含选自碳和氧的元素并与第一子层接触的金属化合物。

公开(公告)号：US20200098883A1

公开(公告)日：2020-03-26

申请号：US16692053

申请日：2019-11-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shiu-Ko JangJian ,  Chi-Wen Liu ,  Chih-Nan Wu ,  Chun Che Lin

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L21/8238

摘要： Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.

公开(公告)号：US20200066911A1

公开(公告)日：2020-02-27

申请号：US16668871

申请日：2019-10-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Nan Wu ,  Shiu-Ko JangJian ,  Chun Che Lin ,  Wen-Cheng Hsuku

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/423 ,  H01L23/485 ,  H01L21/768 ,  H01L29/51 ,  H01L21/321 ,  H01L29/417

摘要： An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.