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公开(公告)号：US20210356515A1
公开(公告)日：2021-11-18
申请号：US16618928
申请日：2019-05-10
Inventor： Zhixiong JIANG , Yanhong MENG
Abstract: A display panel is provided. A first metal layer is patterned to form a first electrode and a second metal layer is patterned to form a second electrode. A projection of the second electrode and a projection of the first electrode are overlapped on a substrate. A gate insulating layer is disposed between the first metal layer and the second metal layer. A test circuit layer is electrically connected to the second electrode. An electrostatic test electrode includes a first test electrode and a second test electrode. The first test electrode is electrically connected to the first electrode and the second test electrode is electrically connected to the test circuit layer. The gate insulating layer disposed in an intermediate region has an antistatic ability.
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公开(公告)号：US20230215872A1
公开(公告)日：2023-07-06
申请号：US17600254
申请日：2021-08-30
Inventor： Zhixiong JIANG
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1237 , H01L27/1218 , H01L27/1222 , H01L27/127
Abstract: An array substrate, a method for manufacturing an array substrate, and a display panel are provided. The array substrate includes a substrate and a thin film transistor layer arranged on the substrate. The thin film transistor layer includes a plurality of thin film transistors. The thin film transistors each include an active layer, a source/drain, a first gate, a second gate, and a first insulating layer. The first gate and the second gate are electrically connected through the through hole. The problems of difficulty in etching and excessively long etching time are avoided while reducing the gate resistance of the thin film transistor.
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公开(公告)号：US20210012694A1
公开(公告)日：2021-01-14
申请号：US16616971
申请日：2019-11-12
Inventor： Zhixiong JIANG , Yanhong MENG
IPC: G09G3/20
Abstract: The present disclosure provides a stage-number reduced gate driver on array (GOA) circuit and a display device. The circuit includes one or more stages of GOA sub-circuits. Each stage of GOA sub-circuits includes a gate signal input end, an original output end, one or more sub-output ends, and one or more branching devices respectively corresponding to the one or more sub-output ends. The gate signal input end and the original output end are respectively connected to a branching node. One end of the one or more branching devices is respectively connected to the branching node. Another end of the one or more branching devices is connected to the corresponding one or more sub-output ends. The present disclosure can solve the problem of excessive length of the GOA circuit in high-resolution model which is not conducive to a narrow bezel design.
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公开(公告)号：US20230161209A1
公开(公告)日：2023-05-25
申请号：US17051457
申请日：2020-05-20
Inventor： Zhixiong JIANG , Sheng SUN , Yoonsung UM , Woosung SON , Meng CHEN , Wuguang LIU , Jubin LI , Zhiwei TAN , Haiyan QUAN , Kaili QU , Chuwei LIANG , Ziqi LIU , Lintao LIU , Ting LI , Sikun HAO
IPC: G02F1/1368 , G02F1/1343 , G02F1/1362 , G02F1/1335 , H01L27/12
CPC classification number: G02F1/1368 , G02F1/134309 , G02F1/136286 , G02F1/133514 , H01L27/1222
Abstract: The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.
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