公开(公告)号：US12242392B2

公开(公告)日：2025-03-04

申请号：US17892693

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Patrick Kruse ,  Gregory Shurtz ,  Denis Beaudoin ,  Abhishek Shankar ,  Daniel Wu

IPC: G06F13/16 ,  G06F12/14

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

公开(公告)号：US11960416B2

公开(公告)日：2024-04-16

申请号：US17558278

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu ,  Abhishek Shankar ,  Mihir Narendra Mody ,  Gregory Raymond Shurtz ,  Jason A. T. Jones ,  Hemant Vijay Kumar Hariyani

IPC: G06F13/16

CPC classification number: G06F13/1647

Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

公开(公告)号：US20230401164A1

公开(公告)日：2023-12-14

申请号：US17892693

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Patrick Kruse ,  Gregory Shurtz ,  Denis Beaudoin ,  Abhishek Shankar ,  Daniel Wu

IPC: G06F12/14 ,  G06F13/16

CPC classification number: G06F12/1416 ,  G06F13/1668 ,  G06F2212/1052

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.