公开(公告)号：US20230401164A1

公开(公告)日：2023-12-14

申请号：US17892693

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Patrick Kruse ,  Gregory Shurtz ,  Denis Beaudoin ,  Abhishek Shankar ,  Daniel Wu

IPC: G06F12/14 ,  G06F13/16

CPC classification number: G06F12/1416 ,  G06F13/1668 ,  G06F2212/1052

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

公开(公告)号：US10396922B2

公开(公告)日：2019-08-27

申请号：US15891227

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Eric Hansen ,  Denis Beaudoin ,  Thomas Anton Leyrer

IPC: H04J3/06 ,  H04L7/00

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US12113612B2

公开(公告)日：2024-10-08

申请号：US17876662

申请日：2022-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Eric Hansen ,  Denis Beaudoin ,  Thomas Anton Leyrer

IPC: H04J3/06 ,  H04L7/00

CPC classification number: H04J3/0658 ,  H04J3/0641 ,  H04J3/0676 ,  H04J3/0679 ,  H04J3/0691 ,  H04J3/0667 ,  H04J3/0688 ,  H04L7/0083

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US10735700B2

公开(公告)日：2020-08-04

申请号：US16438876

申请日：2019-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: H04N9/04 ,  G06T3/40 ,  G06T5/00

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US20190295220A1

公开(公告)日：2019-09-26

申请号：US16438876

申请日：2019-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: G06T3/40 ,  H04N9/04

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US09141561B2

公开(公告)日：2015-09-22

申请号：US13672082

申请日：2012-11-08

Applicant: Texas Instruments Incorporated

Inventor： Serge Bernard Lasserre ,  Marouane Berrada ,  Stephen Busch ,  Denis Beaudoin

IPC: G06F12/00 ,  G06F13/00 ,  G11C11/406

CPC classification number: G06F13/00 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

Abstract: A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands.

Abstract translation: 系统包括多个主设备和至少一个存储器刷新调度器。 当主设备需要更高优先级的存储器访问时，主设备向存储器刷新调度器发送动态优先级信号，作为响应，存储器刷新调度器改变用于发出刷新命令的策略。

公开(公告)号：US12242392B2

公开(公告)日：2025-03-04

申请号：US17892693

申请日：2022-08-22

Applicant: Texas Instruments Incorporated

Inventor： Patrick Kruse ,  Gregory Shurtz ,  Denis Beaudoin ,  Abhishek Shankar ,  Daniel Wu

IPC: G06F13/16 ,  G06F12/14

Abstract: An example apparatus includes: bandwidth estimator circuitry configured to: obtain a first memory transaction; and determine a consumed bandwidth associated with the memory transaction; and gate circuitry configured to: permit transmission of the memory transaction to a memory controller circuitry; determine whether to gate a second memory transaction generated by a source of the first memory transaction based on the consumed bandwidth of the first memory transaction; and when it is determined to gate the second memory transaction, prevent transmission of the second memory transaction for an amount of time based on the consumed bandwidth.

公开(公告)号：US11463664B2

公开(公告)日：2022-10-04

申请号：US16911579

申请日：2020-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: H04N9/04 ,  G06T3/40 ,  G06T5/00

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US11949995B2

公开(公告)日：2024-04-02

申请号：US17895191

申请日：2022-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: H04N23/84 ,  G06T3/40 ,  G06T3/4015 ,  G06T3/403 ,  G06T5/00 ,  H04N25/13 ,  H04N25/131

CPC classification number: H04N23/843 ,  G06T3/4015 ,  G06T3/403 ,  G06T5/00 ,  G06T2207/20012 ,  G06T2207/20192 ,  H04N25/131 ,  H04N25/134 ,  H04N25/135 ,  H04N2209/046

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US10366471B2

公开(公告)日：2019-07-30

申请号：US15349609

申请日：2016-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: G06T3/40 ,  H04N9/04

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.