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    Pipelined read-modify-write operations in cache memory
    3.
    发明授权
    Pipelined read-modify-write operations in cache memory 有权

    公开(公告)号：US11609818B2

    公开(公告)日：2023-03-21

    申请号：US17588448

    申请日：2022-01-31

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

    IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

    Multichannel memory arbitration and interleaving scheme
    5.
    发明授权
    Multichannel memory arbitration and interleaving scheme 有权

    公开(公告)号：US11960416B2

    公开(公告)日：2024-04-16

    申请号：US17558278

    申请日：2021-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad Wu ,  Abhishek Shankar ,  Mihir Narendra Mody ,  Gregory Raymond Shurtz ,  Jason A. T. Jones ,  Hemant Vijay Kumar Hariyani

    IPC: G06F13/16

    CPC classification number: G06F13/1647

    Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

    WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
    6.
    发明申请
    WRITE CONTROL FOR READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY 审中-公开

    公开(公告)号：US20200371918A1

    公开(公告)日：2020-11-26

    申请号：US16874516

    申请日：2020-05-14

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

    IPC: G06F12/0811 ,  G06F12/0815 ,  G06F3/06 ,  G06F9/38 ,  G06F12/126

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

    PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY
    10.
    发明申请
    PIPELINED READ-MODIFY-WRITE OPERATIONS IN CACHE MEMORY 有权

    公开(公告)号：US20220156149A1

    公开(公告)日：2022-05-19

    申请号：US17588448

    申请日：2022-01-31

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

    IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

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