公开(公告)号：US20160027647A1

公开(公告)日：2016-01-28

申请号：US14874234

申请日：2015-10-02

Applicant: Texas Instruments Incorporated

Inventor： Xiang-Zheng Bo ,  Alwin Tsao ,  Douglas T. Grider

IPC: H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/266

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract translation: 包含模拟MOS晶体管的集成电路可以通过以正好四个子植入物注入漏极延伸来形成，其中至少一个子注入在模拟MOS晶体管的源极/漏极栅极边缘处将集成电路的衬底中的掺杂物注入 对于模拟MOS晶体管的每个源极/漏极栅极边缘，相对于模拟MOS晶体管的源极/漏极栅极边缘具有5度至40度的幅度的扭曲角，其中零扭转角子植入物是垂直的 到源极/漏极栅极边缘。 在模拟MOS晶体管的任何源/漏极边缘处，不超过两个子植入物将掺杂剂放置在衬底中。 所有四个子植入物以相同的倾斜角度执行。 在模拟MOS晶体管上不进行光晕注入。

公开(公告)号：US20140187008A1

公开(公告)日：2014-07-03

申请号：US14142251

申请日：2013-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiang-Zheng Bo ,  Alwin Tsao ,  Douglas T. Grider

IPC: H01L21/266 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract translation: 包含模拟MOS晶体管的集成电路可以通过以正好四个子植入物注入漏极延伸来形成，其中至少一个子注入在模拟MOS晶体管的源极/漏极栅极边缘处将集成电路的衬底中的掺杂物注入 对于模拟MOS晶体管的每个源极/漏极栅极边缘，相对于模拟MOS晶体管的源极/漏极栅极边缘具有5度至40度的幅度的扭曲角，其中零扭转角子植入物是垂直的 到源极/漏极栅极边缘。 在模拟MOS晶体管的任何源/漏极边缘处，不超过两个子植入物将掺杂剂放置在衬底中。 所有四个子植入物以相同的倾斜角度执行。 在模拟MOS晶体管上不进行光晕注入。

公开(公告)号：US09431248B2

公开(公告)日：2016-08-30

申请号：US14874234

申请日：2015-10-02

Applicant: Texas Instruments Incorporated

Inventor： Xiang-Zheng Bo ,  Alwin Tsao ,  Douglas T. Grider

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

公开(公告)号：US20210089694A1

公开(公告)日：2021-03-25

申请号：US16944890

申请日：2020-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Murlidhar Bashyam ,  Alwin Tsao ,  Douglas Newman

IPC: G06F30/367 ,  H01L21/66 ,  G06F30/398 ,  G06F30/392 ,  G06F30/373 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

公开(公告)号：US11455452B2

公开(公告)日：2022-09-27

申请号：US16944890

申请日：2020-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Murlidhar Bashyam ,  Alwin Tsao ,  Douglas Newman

IPC: G06F30/30 ,  G06F30/367 ,  H01L21/66 ,  G06F30/398 ,  G06F30/392 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  G06F30/373

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

公开(公告)号：US09177802B2

公开(公告)日：2015-11-03

申请号：US14142251

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Xiang-Zheng Bo ,  Alwin Tsao ,  Douglas T. Grider

IPC: H01L21/336 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/6659

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract translation: 包含模拟MOS晶体管的集成电路可以通过以正好四个子植入物注入漏极延伸来形成，其中至少一个子注入在模拟MOS晶体管的源极/漏极栅极边缘处将集成电路的衬底中的掺杂物注入 对于模拟MOS晶体管的每个源极/漏极栅极边缘，相对于模拟MOS晶体管的源极/漏极栅极边缘具有5度至40度的幅度的扭曲角，其中零扭转角子植入物是垂直的 到源极/漏极栅极边缘。 在模拟MOS晶体管的任何源/漏极边缘处，不超过两个子植入物将掺杂剂放置在衬底中。 所有四个子植入物以相同的倾斜角度执行。 在模拟MOS晶体管上不进行光晕注入。