公开(公告)号：US20210089694A1

公开(公告)日：2021-03-25

申请号：US16944890

申请日：2020-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Murlidhar Bashyam ,  Alwin Tsao ,  Douglas Newman

IPC: G06F30/367 ,  H01L21/66 ,  G06F30/398 ,  G06F30/392 ,  G06F30/373 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

公开(公告)号：US11455452B2

公开(公告)日：2022-09-27

申请号：US16944890

申请日：2020-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Murlidhar Bashyam ,  Alwin Tsao ,  Douglas Newman

IPC: G06F30/30 ,  G06F30/367 ,  H01L21/66 ,  G06F30/398 ,  G06F30/392 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  G06F30/373

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

公开(公告)号：US20170345780A1

公开(公告)日：2017-11-30

申请号：US15162867

申请日：2016-05-24

Applicant: Texas Instruments Incorporated

Inventor： Murlidhar Bashyam ,  Richard Allen Faust

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/02074 ,  H01L24/05 ,  H01L2224/03466 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05686 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A plasma-based ashing process for surface conditioning and material modification to improve bond pad metallurgical properties as well as semiconductor device performance. Residue materials generated in a removal process at a process layer having recessed features with Ni—Pd surfaces are ashed in a plasma reactor to reduce defect count and improve surface conditioning associated with bond pads of the semiconductor device.