公开(公告)号：US20250048724A1

公开(公告)日：2025-02-06

申请号：US18921317

申请日：2024-10-21

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US12009423B2

公开(公告)日：2024-06-11

申请号：US17135541

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Edward Hornung ,  Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/167 ,  H01L29/66492

Abstract: An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

公开(公告)号：US20220189954A1

公开(公告)日：2022-06-16

申请号：US17117421

申请日：2020-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225 ,  H01L21/8234

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US11205575B2

公开(公告)日：2021-12-21

申请号：US16552321

申请日：2019-08-27

Applicant: Texas Instruments Incorporated

Inventor： Byron Joseph Palla ,  Stephen Alan Keller ,  Brian Edward Hornung ,  Brian K. Kirkpatrick ,  Douglas Ticknor Grider

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/762 ,  H01L27/105 ,  H01L27/11573

Abstract: A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

公开(公告)号：US11616058B2

公开(公告)日：2023-03-28

申请号：US17117421

申请日：2020-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US20220209012A1

公开(公告)日：2022-06-30

申请号：US17135541

申请日：2020-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Edward Hornung ,  Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/167 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

公开(公告)号：US20200343099A1

公开(公告)日：2020-10-29

申请号：US16552321

申请日：2019-08-27

Applicant: Texas Instruments Incorporated

Inventor： Byron Joseph Palla ,  Stephen Alan Keller ,  Brian Edward Hornung ,  Brian K. Kirpatrick ,  Douglas Ticknor Grider

IPC: H01L21/311

Abstract: A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

公开(公告)号：US12154901B2

公开(公告)日：2024-11-26

申请号：US18188812

申请日：2023-03-23

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

公开(公告)号：US20240304723A1

公开(公告)日：2024-09-12

申请号：US18667347

申请日：2024-05-17

Applicant: Texas Instruments Incorporated

Inventor： Brian Edward Hornung ,  Mahalingam Nandakumar

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/167 ,  H01L29/66492

Abstract: An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.

公开(公告)号：US20230230975A1

公开(公告)日：2023-07-20

申请号：US18188812

申请日：2023-03-23

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Edward Hornung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823418 ,  H01L27/088 ,  H01L29/7833 ,  H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266

Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.