公开(公告)号：US20200252076A1

公开(公告)日：2020-08-06

申请号：US16856167

申请日：2020-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03M1/20

Abstract: A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.

公开(公告)号：US20250023575A1

公开(公告)日：2025-01-16

申请号：US18524652

申请日：2023-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya Appala PENTAKOTA ,  Sai Vikas KANDIMALLA ,  Neeraj SHRIVASTAVA ,  Eeshan MIGLANI

IPC: H03M1/10

Abstract: An analog-to-digital converter (ADC) includes: a time-domain ADC core; and a calibration circuit. The time-domain ADC core includes: a first delay-to-digital stage having a terminal; a second delay-to-digital stage having a terminal; a third delay-to-digital stage having a terminal. The calibration circuitry is coupled to the terminal of the first delay-to-digital stage, the terminal of the second delay-to-digital stage, and the terminal of the third delay-to-digital stage of stages. The calibration circuitry is configured to calibrate the first delay-to-digital stage, the second delay-to-digital stage, and the third delay-to-digital stage based on a zero-crossing calibration and an over-range calibration. The over-range calibration sets a maximum threshold and a minimum threshold for the time-domain ADC relative to a reference voltage.

公开(公告)号：US20210336630A1

公开(公告)日：2021-10-28

申请号：US17366506

申请日：2021-07-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03M1/20

Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

公开(公告)号：US20190222207A1

公开(公告)日：2019-07-18

申请号：US16364239

申请日：2019-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03K5/24 ,  H03M1/50

CPC classification number: H03K5/249 ,  H03K2005/00215 ,  H03M1/50

Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

公开(公告)号：US20210184665A1

公开(公告)日：2021-06-17

申请号：US17181073

申请日：2021-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03K5/24 ,  H03M1/50

Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

公开(公告)号：US20200259501A1

公开(公告)日：2020-08-13

申请号：US16860145

申请日：2020-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala PENTAKOTA ,  Rishi SOUNDARARAJAN ,  Shagun DUSAD ,  Chirag Chandrahas SHETTY

IPC: H03M1/38 ,  H03K5/24

Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.