公开(公告)号：US20200059311A1

公开(公告)日：2020-02-20

申请号：US16552353

申请日：2019-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20250030494A1

公开(公告)日：2025-01-23

申请号：US18909428

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06 ,  H04L7/00

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20220368444A1

公开(公告)日：2022-11-17

申请号：US17876662

申请日：2022-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

公开(公告)号：US20180227067A1

公开(公告)日：2018-08-09

申请号：US15891227

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua HU ,  Venkateswar Reddy KOWKUTLA ,  Eric HANSEN ,  Denis BEAUDOIN ,  Thomas Anton LEYRER

IPC: H04J3/06

CPC classification number: H04J3/0658 ,  H04J3/0641 ,  H04J3/0667 ,  H04J3/0676 ,  H04J3/0679 ,  H04J3/0688 ,  H04J3/0691 ,  H04L7/0083

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.