METHODS TO REDUCE MEASURE CURRENT SETTLING TIME IN SMU

    公开(公告)号:US20240356492A1

    公开(公告)日:2024-10-24

    申请号:US18240564

    申请日:2023-08-31

    CPC classification number: H03F1/0211 H03F2200/144 H03F2200/462 H03F2200/471

    Abstract: The techniques and circuits, described herein, include solutions for reducing measure current settling time in source measurement units (SMUs) during a force voltage mode of operation. An SMU includes a force amplifier having a first voltage input, a second voltage input, a feedback voltage input, and a output. A resistor has a first terminal coupled to the output of the force amplifier, and a second terminal. A switch is coupled between the second terminal of the resistor and the feedback voltage input of the force amplifier. The switch is closed in the force voltage mode, creating a feedback path which the resistor is contained within. A series combination of a capacitor and a resistor is coupled to a gate of a transistor within the force amplifier, which results in improved measure current settling time compared to alternative techniques.

    FORCE/MEASURE CURRENT GAIN TRIMMING
    2.
    发明公开

    公开(公告)号:US20240337686A1

    公开(公告)日:2024-10-10

    申请号:US18478038

    申请日:2023-09-29

    Abstract: The techniques and circuits, described herein, include solutions for error compensation in source measurement units (SMUs). An example SMU is capable of both sourcing current to a device under test (DUT) and measuring current through the DUT. An SMU may include a sensing resistor coupled in series with the DUT. A voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the DUT. In practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. A gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the DUT can be sourced and measured.

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