公开(公告)号：US20240334692A1

公开(公告)日：2024-10-03

申请号：US18193899

申请日：2023-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Zeng Zhang ,  Jack Qian ,  Keith Jarreau ,  Tamer San ,  Mark Eskew

IPC: H10B41/30 ,  H01L29/788 ,  H10B20/25 ,  H10B41/10

CPC classification number: H10B41/30 ,  H01L29/788 ,  H10B20/25 ,  H10B41/10

Abstract: An integrated circuit comprises a transistor extending into a semiconductor substrate and having a gate structure having major and minor axes parallel to a surface of the semiconductor substrate, and a UV-opaque sheet structure vertically spaced apart from a top surface of the gate structure by a first distance and including an opening, the opening having first and second sides about parallel to the major axis, at least one of the first and second sides laterally spaced apart from a corresponding side of the gate structure by a second distance that is less than or equal to the first distance.

公开(公告)号：US20250048656A1

公开(公告)日：2025-02-06

申请号：US18228338

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jack Qian ,  Kemal Tamer San ,  Guruvayurappan S. Mathur

IPC: H10B99/00 ,  H10B20/20

Abstract: Described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. Each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. A first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.

公开(公告)号：US20250081449A1

公开(公告)日：2025-03-06

申请号：US18240580

申请日：2023-08-31

Applicant: Texas Instruments Incorporated

Inventor： Jack Qian ,  Doug Weiser ,  Tamer San

IPC: H10B20/25 ,  G11C17/16 ,  G11C17/18

Abstract: An electronic device with a non-volatile memory includes a non-volatile memory (NVM) cell selectively programmable to change a program state from a first state to a second state or to a third state, and may also include a write circuit configured to selectively program the NVM cell to change the program state from the first state to the second state by applying a programming voltage signal to a first source/drain region and to change the program state from the first state to the third state by applying the programming voltage signal to a second source/drain region. A read circuit is configured to identify the program state of the NVM memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.