公开(公告)号：US09548377B2

公开(公告)日：2017-01-17

申请号：US14273704

申请日：2014-05-09

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Kemal Tamer San

IPC: H01L29/66 ,  H01L21/324 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L29/66477 ,  H01L21/324 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/66659

Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.

Abstract translation: 包括MOS晶体管和铁电电容器在内的集成电路的制造中的半导体晶片的热处理，包括使用钛酸铅锆（PZT）铁电材料的半导体晶片，以减少晶体管的电特性的变化。 在晶体管和电容器形成之后，在基本不存在氢的含氮气氛中对晶片进行热处理。 可以在沉积铁电处理之前，在含氢气氛中对晶片进行可选的热处理。

公开(公告)号：US12150298B2

公开(公告)日：2024-11-19

申请号：US17515147

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Anand Seshadri ,  Kemal Tamer San ,  Sunil Kumar Dusa ,  Michael Ball ,  Akram A. Salman

IPC: H01L21/00 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H10B20/20

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

公开(公告)号：US20250048656A1

公开(公告)日：2025-02-06

申请号：US18228338

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jack Qian ,  Kemal Tamer San ,  Guruvayurappan S. Mathur

IPC: H10B99/00 ,  H10B20/20

Abstract: Described examples include an integrated circuit having a plurality of nominally identical polycrystalline silicon resistors over a semiconductor substrate. Each of the polysilicon resistors has a resistor body with a first end and a second end, wherein the first end is connected to a current source and the second end is connected to a resistance discriminator. A first proper subset of the resistors have a first resistance, and a second first proper subset of the resistors have a difference second resistance.

公开(公告)号：US20180374861A1

公开(公告)日：2018-12-27

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillemo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US20160086960A1

公开(公告)日：2016-03-24

申请号：US14728683

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/78 ,  H01L23/31 ,  H01L23/29 ,  H01L21/326 ,  H01L23/00

CPC classification number: H01L27/11507 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02197 ,  H01L21/02318 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/07025 ,  H01L2924/014

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Abstract translation: 固化施加到铁电集成电路的表面的钝化层，以增强铁电结构的极化特性。 在制造有源器件之后，将钝化层（例如聚酰亚胺）施加到铁电集成电路的表面。 钝化层通过暴露于低于铁电材料的居里温度的高温固化，持续时间短，例如十分钟左右。 可以使用变频微波能量来实现这种固化。 固化的钝化层达到拉伸应力状态，结果赋予了下伏的铁电材料的压应力。 在固化过程之前极化铁电材料可以进一步提高极化。

公开(公告)号：US20230138308A1

公开(公告)日：2023-05-04

申请号：US17515147

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Anand Seshadri ,  Kemal Tamer San ,  Sunil Kumar Dusa ,  Michael Ball ,  Akram A. Salman

IPC: H01L27/112 ,  H01L23/525 ,  G11C17/18 ,  G11C17/16

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

公开(公告)号：US11495607B2

公开(公告)日：2022-11-08

申请号：US16056827

申请日：2018-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huang-Chun Wen ,  Richard Allen Bailey ,  Antonio Guillermo Acosta ,  John A. Rodriguez ,  Scott Robert Summerfelt ,  Kemal Tamer San

IPC: H01L27/11507 ,  H01L21/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

公开(公告)号：US20150079698A1

公开(公告)日：2015-03-19

申请号：US14273704

申请日：2014-05-09

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Kemal Tamer San

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/66477 ,  H01L21/324 ,  H01L27/11507 ,  H01L28/57 ,  H01L29/66659

Abstract: Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed.

Abstract translation: 包括MOS晶体管和铁电电容器在内的集成电路的制造中的半导体晶片的热处理，包括使用钛酸铅锆（PZT）铁电材料的半导体晶片，以减少晶体管的电特性的变化。 在晶体管和电容器形成之后，在基本不存在氢的含氮气氛中对晶片进行热处理。 可以在沉积铁电处理之前，在含氢气氛中对晶片进行可选的热处理。