公开(公告)号：US20250006573A1

公开(公告)日：2025-01-02

申请号：US18345186

申请日：2023-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Maricel Fabia ESCAÑO ,  Katleen Fajardo TIMBOL ,  Jeffrey Salvacion SOLAS

IPC: H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: In examples, a semiconductor package comprises a semiconductor die including a device side having circuitry formed therein. The device side includes a sensor. The package includes a metal member creating a hollow cavity extending through the metal member, the hollow cavity vertically aligned with the sensor, the metal member including a lower portion having a first wall thickness and an upper portion having varying wall thicknesses greater than and less than the first wall thickness, an intersection of the upper and lower portions forming a notch on an outer side of the metal member opposing the hollow cavity. The package also includes a mold compound covering portions of the semiconductor die and contacting the metal member.

公开(公告)号：US20250140735A1

公开(公告)日：2025-05-01

申请号：US18498126

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jomari AUSTRIA ,  Ray Fredric DE ASIS ,  Jeffrey Salvacion SOLAS

IPC: H01L23/00

Abstract: A package comprises a semiconductor die including a device side having circuitry formed therein. The package includes a metal member coupled to the device side and a nanotwin copper member having a bottom surface coupled to the metal member, the nanotwin copper member comprising a twin boundary separating a first region having a first grain structure from a second region having a second grain structure. The package also comprises a wire bond coupled directly to a top surface of the nanotwin copper member, the wire bond contacting multiple regions of the nanotwin copper member. The package also comprises a mold compound covering the die, the metal member, the nanotwin copper member, and the wire bond.

公开(公告)号：US20240234282A1

公开(公告)日：2024-07-11

申请号：US18617499

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Salvacion SOLAS ,  Maricel Fabia ESCAÑO

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481

Abstract: In some examples a method comprises forming an insulating member over a circuit on a device side of a semiconductor die, removing a portion of the insulating member to produce a cavity, and forming a seed layer on the insulating member and within the cavity. In addition, the method includes forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials. Further, the method includes removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member.

公开(公告)号：US20250140718A1

公开(公告)日：2025-05-01

申请号：US18498144

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jose Arvin M. PLOMANTES ,  Jeffrey Salvacion SOLAS

IPC: H01L23/00

Abstract: A package comprises a semiconductor die including a device side having circuitry formed therein and a first metal member on the device side of the die and having a top surface facing away from the die. The first metal member includes a group of dielectric members, each dielectric member in the group of dielectric members extending at least partially through a thickness of the first metal member. The package also comprises solder material contacting the top surface of the first metal member and top surfaces of the dielectric members in the group of dielectric members. The package also includes a second metal member coupled to the solder material and to a conductive terminal of the package, the conductive terminal exposed to an exterior of the package.

公开(公告)号：US20230068086A1

公开(公告)日：2023-03-02

申请号：US17463077

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Salvacion SOLAS ,  Maricel Fabia ESCAÑO

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48

Abstract: In some examples a method comprises forming an insulating member over a circuit on a device side of a semiconductor die, removing a portion of the insulating member to produce a cavity, and forming a seed layer on the insulating member and within the cavity. In addition, the method includes forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials. Further, the method includes removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member.