OPEN CAVITY SENSOR
    1.
    发明申请

    公开(公告)号:US20250006573A1

    公开(公告)日:2025-01-02

    申请号:US18345186

    申请日:2023-06-30

    Abstract: In examples, a semiconductor package comprises a semiconductor die including a device side having circuitry formed therein. The device side includes a sensor. The package includes a metal member creating a hollow cavity extending through the metal member, the hollow cavity vertically aligned with the sensor, the metal member including a lower portion having a first wall thickness and an upper portion having varying wall thicknesses greater than and less than the first wall thickness, an intersection of the upper and lower portions forming a notch on an outer side of the metal member opposing the hollow cavity. The package also includes a mold compound covering portions of the semiconductor die and contacting the metal member.

    CAVITY INTEGRATED CIRCUIT
    2.
    发明申请

    公开(公告)号:US20250069976A1

    公开(公告)日:2025-02-27

    申请号:US18455163

    申请日:2023-08-24

    Abstract: An electronic device includes a substrate and a die having an active surface disposed on the substrate. A sensor is in communication with the active surface of the die and a ring is disposed on the die and encircles the sensor. The ring includes a cylindrical wall and a cap, where the cylindrical wall has an open top and the cap has a partial circular shape that extends beyond each side of the cylindrical wall, A cover is disposed on the cap such that the cover closes off the open top of the ring to form a cavity inside the ring to prevent foreign substance from entering the cavity. A mold compound covers the die and the cover, and abuts an outer surface of the cylindrical wall.

    PACKAGES WITH LOW-PROFILE POLYIMIDE LAYERS

    公开(公告)号:US20250096156A1

    公开(公告)日:2025-03-20

    申请号:US18470321

    申请日:2023-09-19

    Abstract: In examples, a package comprises a semiconductor die having a device side comprising circuitry formed therein. The package comprises a planarized passivation layer abutting the device side and a horizontal metal member coupled to the device side by way of vias extending through the passivation layer. The horizontal metal member has a thickness ranging between 4 microns and 25 microns. The package also comprises a metal post coupled to and vertically aligned with the horizontal metal member without a sputtered seed layer between the metal post and the horizontal metal member. The metal post has a vertical thickness ranging between 10 microns and 80 microns. The package also comprises a polyimide (PI) layer contacting the metal post, the horizontal metal member, and the passivation layer. The PI layer is not positioned between the metal post and the horizontal metal member. A thickness of a thickest portion of the PI layer ranges between 3 microns and 80 microns.

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