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公开(公告)号:US20230036643A1
公开(公告)日:2023-02-02
申请号:US17390823
申请日:2021-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mahmud Halim CHOWDHURY , Amin SIJELMASSI , Murali KITTAPPA , Anindya PODDAR , Honglin GUO , Joe Adam GARCIA , John Paul TELLKAMP
Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.
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公开(公告)号:US20240332243A1
公开(公告)日:2024-10-03
申请号:US18740456
申请日:2024-06-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mahmud Halim CHOWDHURY , Amin SIJELMASSI , Murali KITTAPPA , Anindya PODDAR , Honglin GUO , Joe Adam GARCIA , John Paul TELLKAMP
IPC: H01L23/00 , H01H85/02 , H01L23/495 , H01L23/498
CPC classification number: H01L24/48 , H01H85/0241 , H01L24/49 , H01L24/85 , H01H2085/0283 , H01L23/49555 , H01L23/49827 , H01L24/73 , H01L2224/4801 , H01L2224/48175 , H01L2224/48227 , H01L2224/48455 , H01L2224/4846 , H01L2224/48479 , H01L2224/48499 , H01L2224/49111 , H01L2224/494 , H01L2224/73265 , H01L2224/85051 , H01L2224/85186 , H01L2224/8534 , H01L2924/01013 , H01L2924/01079 , H01L2924/2064 , H01L2924/2075
Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.
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公开(公告)号:US20190206741A1
公开(公告)日:2019-07-04
申请号:US15858862
申请日:2017-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Anindya PODDAR , Usman Mahmood CHAUDHRY , Tran Kiet THU , Mahmud Halim CHOWDHURY , Peter SMEYS
IPC: H01L21/8234 , H01L21/762 , H01L21/304 , H01L27/088 , H01L23/31
CPC classification number: H01L21/823481 , H01L21/3043 , H01L21/76224 , H01L21/823425 , H01L21/823487 , H01L23/3178 , H01L27/088
Abstract: In one aspect of the disclosure, an integrated circuit is disclosed. The integrated circuit includes a first FET device formed on a substrate having a first source, a first gate, and a first channel. The first channel is formed in the substrate, connecting the first source to a common drain. The integrated circuit also includes a second FET device formed on the substrate having a second source, a second gate, and a second channel. The second channel is formed in the substrate, connecting the second source to the common drain. A trench is formed in the substrate between the first channel and the second channel.
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