PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING

    公开(公告)号:US20230100911A1

    公开(公告)日:2023-03-30

    申请号:US17488586

    申请日:2021-09-29

    Abstract: An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to the surface and a bond pad on the surface and coupled to the device. The cap wafer is bonded to the device substrate and partially diced at the first and second dicing grooves such that the bond pad is exposed. Aligning the cap wafer and the device substrate includes aligning the first and second dicing grooves between the bond pad and a bonding area at which the cap wafer is bonded to the device substrate. A width of the first and second dicing grooves prevents cap wafer dust formed during the partial dicing from falling on the bond pad.

    LAMB WAVE RESONATOR-BASED TORQUE SENSOR
    5.
    发明申请

    公开(公告)号:US20200186120A1

    公开(公告)日:2020-06-11

    申请号:US16509224

    申请日:2019-07-11

    Abstract: A torque sensor chip including a semiconductor substrate, an acoustic reflector formed on the semiconductor substrate, and first and second Lamb wave resonators (LWRs). The first LWR is formed on a side of the acoustic reflector opposite the semiconductor substrate. The first LWR is at a first angle with respect to an axis of the IC. The second LWR also is formed on the side of the acoustic reflector opposite the semiconductor substrate. The second LWR is at a second angle, different than the first angle, with respect to the axis of the IC.

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