公开(公告)号：US10581426B1

公开(公告)日：2020-03-03

申请号：US16297963

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: G05F1/00 ,  H02M3/335 ,  H03K17/14 ,  H01L25/16 ,  H01L21/8249 ,  H01L27/06

Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.

公开(公告)号：US20250142866A1

公开(公告)日：2025-05-01

申请号：US18783955

申请日：2024-07-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Zhikai Tang ,  Masahiko Higashi ,  Ujwal Radhakrishna ,  Jungwoo Joh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor processing for a self-aligned gate structure and corresponding semiconductor device. In an example, a semiconductor device includes a semiconductor substrate, a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is over the semiconductor substrate. The offset dielectric layer is over the semiconductor gate layer. The gate metal contact is over the offset dielectric layer and is through an opening through the offset dielectric layer. The gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. A first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned over the semiconductor substrate.

公开(公告)号：US20200295748A1

公开(公告)日：2020-09-17

申请号：US16794275

申请日：2020-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: H03K17/14 ,  H01L25/16 ,  H01L21/8249 ,  H01L27/06

Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.

公开(公告)号：US10812064B2

公开(公告)日：2020-10-20

申请号：US16794275

申请日：2020-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/74 ,  H01L29/76 ,  H03K17/14 ,  H01L25/16 ,  H01L21/8249

Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.