公开(公告)号：US20200295748A1

公开(公告)日：2020-09-17

申请号：US16794275

申请日：2020-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: H03K17/14 ,  H01L25/16 ,  H01L21/8249 ,  H01L27/06

Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.

公开(公告)号：US20190173464A1

公开(公告)日：2019-06-06

申请号：US15831623

申请日：2017-12-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Scott Edward Ragona ,  Jonathan Almeria Noquil

IPC: H03K17/687 ,  H03K17/16 ,  H03K17/06 ,  H02M3/158

Abstract: One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET.

公开(公告)号：US11195915B2

公开(公告)日：2021-12-07

申请号：US16384700

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Seetharaman Sridhar

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.

公开(公告)号：US10581426B1

公开(公告)日：2020-03-03

申请号：US16297963

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: G05F1/00 ,  H02M3/335 ,  H03K17/14 ,  H01L25/16 ,  H01L21/8249 ,  H01L27/06

Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.

公开(公告)号：US10826487B2

公开(公告)日：2020-11-03

申请号：US15831623

申请日：2017-12-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Scott Edward Ragona ,  Jonathan Almeria Noquil

IPC: H02M3/158 ,  H03K17/687 ,  H03K17/16 ,  H03K17/06 ,  H03K17/0412

Abstract: One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET.

公开(公告)号：US10812064B2

公开(公告)日：2020-10-20

申请号：US16794275

申请日：2020-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/74 ,  H01L29/76 ,  H03K17/14 ,  H01L25/16 ,  H01L21/8249

Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.