LOOP DELAY COMPENSATION IN A DELTA-SIGMA MODULATOR

    公开(公告)号:US20210099186A1

    公开(公告)日:2021-04-01

    申请号:US16911702

    申请日:2020-06-25

    Inventor: Meghna AGRAWAL

    Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor hays a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

    COMPENSATED DIGITAL-TO-ANALOG CONVERTER (DAC)

    公开(公告)号:US20240267053A1

    公开(公告)日:2024-08-08

    申请号:US18639466

    申请日:2024-04-18

    CPC classification number: H03M1/0617 H03M3/464

    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.

    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH EMBEDDED FILTERING

    公开(公告)号:US20220407537A1

    公开(公告)日:2022-12-22

    申请号:US17893076

    申请日:2022-08-22

    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

    LOOP DELAY COMPENSATION IN A DELTA-SIGMA MODULATOR

    公开(公告)号:US20210351783A1

    公开(公告)日:2021-11-11

    申请号:US17380356

    申请日:2021-07-20

    Inventor: Meghna AGRAWAL

    Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH EMBEDDED FILTERING

    公开(公告)号:US20240113724A1

    公开(公告)日:2024-04-04

    申请号:US18535445

    申请日:2023-12-11

    CPC classification number: H03M1/462 H03M1/0626 H03M1/182 H03M1/468

    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

    COMPENSATED DIGITAL-TO-ANALOG CONVERTER (DAC)

    公开(公告)号:US20230047618A1

    公开(公告)日:2023-02-16

    申请号:US17967815

    申请日:2022-10-17

    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.

    COMPENSATED DIGITAL-TO-ANALOG CONVERTER (DAC)

    公开(公告)号:US20220345138A1

    公开(公告)日:2022-10-27

    申请号:US17335667

    申请日:2021-06-01

    Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.

    LOOP DELAY COMPENSATION IN A SIGMA-DELTA MODULATOR

    公开(公告)号:US20210376851A1

    公开(公告)日:2021-12-02

    申请号:US17183433

    申请日:2021-02-24

    Inventor: Meghna AGRAWAL

    Abstract: A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

Patent Agency Ranking